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| MC68HC08AZ32/d MC68HC08AZ32 advance information january 31, 2000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola list of sections 1 list of sections list of sections list of sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . 51 system integration module (sim). . . . . . . . . . . . . . . . . . 69 clock generator module (cgm). . . . . . . . . . . . . . . . . . 91 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 break module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 computer operating properly module (cop) . . . . . . 143 low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . 149 ?motorola, inc., 2000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections MC68HC08AZ32 2 list of sections motorola external interrupt module (irq) . . . . . . . . . . . . . . . . . . 155 serial communications interface module (sci). . . . . 163 serial peripheral interface module (spi) . . . . . . . . . . . 197 timer interface module a (tima) . . . . . . . . . . . . . . . . . 231 timer interface module b (timb) . . . . . . . . . . . . . . . . . 257 programmable interrupt timer (pit) . . . . . . . . . . . . . . . 279 analog-to-digital converter (adc). . . . . . . . . . . . . . . 287 keyboard module (kb) . . . . . . . . . . . . . . . . . . . . . . . . . 299 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 mscan08 controller (mscan08) . . . . . . . . . . . . . . . . . 331 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 appendix a: future eeprom registers . . . . . . . . . . . . 391 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 literature updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola table of contents 3 table of contents table of contents list of sections table of contents general description contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 memory map contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ram contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 rom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 eeprom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 future eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 central processor unit (cpu) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC08AZ32 4 table of contents motorola cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 system integration module (sim) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . .72 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 clock generator module (cgm) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . .114 mask options contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 break module contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 monitor rom (mon) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC08AZ32 motorola table of contents 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 computer operating properly module (cop) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 148 low-voltage inhibit (lvi) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 external interrupt module (irq) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 160 irq status and control register (iscr) . . . . . . . . . . . . . . . . . . . . . . 160 serial communications interface module (sci) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . 180 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 serial peripheral interface module (spi) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC08AZ32 6 table of contents motorola pin name conventions and i/o register addresses . . . . . . . . . . . . . .199 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 timer interface module a (tima) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 tima during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 timer interface module b (timb) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 timb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 programmable interrupt timer (pit) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC08AZ32 motorola table of contents 7 analog-to-digital converter (adc) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 keyboard module (kb) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . 305 i/o ports contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 mscan08 controller (mscan08) contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC08AZ32 8 table of contents motorola programmer? model of message storage . . . . . . . . . . . . . . . . . . . .355 programmer? model of control registers . . . . . . . . . . . . . . . . . . . . .360 specifications contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .380 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 5.0 vdc 0.5v serial peripheral interface (spi) timing . . . . . . . . . .383 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 cgm component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 cgm acquisition/lock time information . . . . . . . . . . . . . . . . . . . . .387 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 appendix a: future eeprom registers eeprom timebase divider control registers . . . . . . . . . . . . . . . .391 eedivh and eedivl registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 eediv non-volatile registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 glossary index literature updates literature distribution centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 customer focus center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 motorola sps world marketing world wide web server . . . . . . . . .418 microcontroller division? web site . . . . . . . . . . . . . . . . . . . . . . . . .418 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola general description 9 general description general description contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power supply pins (vdd and vss) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . 15 external reset pin (rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 external interrupt pin (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 analog power supply pin (vdda) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 analog ground pin (vssa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 analog ground pin (avss/vrefl) . . . . . . . . . . . . . . . . . . . . . . . . . 15 adc voltage reference pin (vrefh) . . . . . . . . . . . . . . . . . . . . . . . 15 analog supply pin (vddaref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 port a input/output (i/o) pins (pta7?ta0) . . . . . . . . . . . . . . . . . . 16 port b i/o pins (ptb7/atd7?tb0/atd0). . . . . . . . . . . . . . . . . . . 16 port c i/o pins (ptc5?tc0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 port d i/o pins (ptd7?td0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 port e i/o pins (pte7/spsck?te0/txd) . . . . . . . . . . . . . . . . . . 16 port f i/o pins (ptf6?tf0/tach2) . . . . . . . . . . . . . . . . . . . . . . . 16 port g i/o pins (ptg2/kbd2?tg0/kbd0) . . . . . . . . . . . . . . . . . . 17 port h i/o pins (pth1/kbd4?th0/kbd3) . . . . . . . . . . . . . . . . . . 17 can transmit pin (cantx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 can receive pin (canrx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 note: this document should not be used for the mc68hc08az48 or mc68hc08az60. these devices have different functionality including a different register set and thus are covered in a separate document, mc68hc08az60/d. 1-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 10 general description motorola introduction the MC68HC08AZ32 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. features features of the MC68HC08AZ32 include the following: high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families 8.4mhz internal bus frequency at 125 c mscan controller (motorola scalable can) (implementing can 2.0b protocol as de?ed in bosch speci?ation sep. 1991) available in 64 qfp package 32,272 bytes user rom user rom data security 512 bytes of on-chip eeprom with security feature 1k byte of on-chip ram serial peripheral interface (spi) module serial communications interface (sci) module 16-bit timer interface module (tima) with four input capture/output compare channels 16-bit timer interface module (timb) with two input capture/output compare channels periodic interrupt timer (pit) 2-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features MC68HC08AZ32 motorola general description 11 clock generator module (cgm) 8-bit, 8- or 15-channel analog to digital convertor module (adc) 5-bit key wakeup port system protection features optional computer operating properly (cop) reset low-voltage detection with optional reset illegal opcode detection with optional reset illegal address detection with optional reset low-power design (fully static with stop and wait modes) master reset pin and power-on reset features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (8 more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications ??language support figure 1 shows the structure of the MC68HC08AZ32 3-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 12 general description motorola . figure 1. MC68HC08AZ32 mcu block diagram pta7-pta0 mscan controller module break module clock generator module system integration module serial peripheral interface module timer1 & 2 interface modules low voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user ram ?1024 bytes user eeprom ?512 bytes user rom ?32,255 bytes monitor rom ?224 bytes irq module power pta ddra ddrb ptb ddrc ptc ddrd ptd ddre pte ptf ddrf ptg ddrg user rom vector space ?48bytes analog to digital convertor module (4 + 2 channels) programmable interrupt timer module serial communications ptb7/atd7-ptb0/atd0 ptc5-ptc3 ptd5/atd13/atd13 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tach1 pte2/tach0 pte1/rxd pte0/txd ptf5/tbch1-ptf4/tbch0 ptf3/tach5-ptf2/tach4 ptf1/tach3 ptf0/tach2 ptg2/kbd2-ptg0/kbd0 vrefh a vss /vre- v ddaref v dd v ss v ssa v dda e vss4 -e vss1 e vdd3 -e vdd1 rst irq osc1 osc2 cgmxfc canrx cantx ptf6 pth ddrh pth1/kbd4-pth0/kbd3 interface module keyboard interrupt module ptc2/mclk ptc1-ptc0 ptd7 ptd6/atd14/taclk ptd4/atd12/tbclk ptd3/atd11/atd11 ptd2/atd10/atd10 ptd1/atd9/atd9- ptd0/atd8/atd8 4-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC08AZ32 motorola general description 13 pin assignments figure 2 shows the 64 qfp pin assignments. figure 2. 64 qfp pin assignments cantx ptf4/tbch0 cgmxfc ptb7/atd7 ptf3 ptf2 ptf1/tach3 ptf0/tach2 rst irq ptc4 canrx ptf5/tbch1 ptf6 pte0/txd pte1/rxd pte2/tach0 pte3/tach1 pth0/kbd3 ptd3/atd11 ptd2/atd10 a vss /vrefl v ddaref ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda vrefh ptd7 ptd6/atd14/taclk ptd5/atd13 ptd4/atd12/tblck pth1/kbd4 ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd ptg0/kbd0 ptg1/kbd1 ptg2/kbd2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MC68HC08AZ32 5-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 14 general description motorola power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 3. shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 3.power supply bypassing v ss is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). note: v ss must be grounded for proper mcu operation. mcu v dd c2 c1 0.1 m f v ss v dd + note: component values shown represent typical applications. 6-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC08AZ32 motorola general description 15 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. see clock generator module (cgm) on page 91. external reset pin (rst ) a ??on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. see system integration module (sim) on page 69. external interrupt pin (irq ) irq is an asynchronous external interrupt pin. see external interrupt module (irq) on page 155. analog power supply pin (v dda ) v dda is the power supply pin for the clock generator module (cgm). analog ground pin (v ssa ) the v ssa analog ground pin is used only for the ground connections for the clock generator module (cgm) section of the circuit and should be decoupled as per the v ss digital ground pin. see clock generator module (cgm) on page 91. analog ground pin (a vss /vrefl) the a vss analog ground pin is used only for the ground connections for the analog to digital convertor (adc) and should be decoupled as per the vss digital ground pin. adc voltage reference pin (vrefh) vrefh is the power supply for setting the reference voltage vrefh. connect the vrefh pin to a voltage potential<= v ddaref , not less than 1.5v. analog supply pin (v ddaref ) the v ddaref analog supply pin is used only for the supply connections for the analog to digital convertor (adc).external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cgm. see clock generator module (cgm) on page 91. 7-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 16 general description motorola port a input/output (i/o) pins (pta7 pta0) pta7?ta0 are general-purpose bidirectional i/o port pins. see i/o ports on page 307. port b i/o pins (ptb7/atd7eptb0/ atd0) port b is an 8-bit special function port that shares all eight pins with the analog to digital convertor (adc). see analog-to-digital converter (adc) on page 287 and i/o ports on page 307. port c i/o pins (ptc5eptc0) ptc5 ptc3 and ptc1 ptc0 are general-purpose bidirectional i/o port pins. ptc2/mclk is a special function port that shares its pin with the system clock. see i/o ports on page 307. port d i/o pins (ptd7eptd0) port d is an 8-bit special function port that shares two of its pins with the timer interface modules (tima and timb). see timer interface module a (tima) on page 231 and timer interface module b (timb) on page 257. ptd6?td0 also share pins with the analog to digital convertor (adc) like port a if the 15-channel adc is selected. port e i/o pins (pte7/spsckepte0/ txd) port e is an 8-bit special function port that shares two of its pins with the timer interface module (tima), four of its pins with the serial peripheral interface module (spi), and two of its pins with the serial communication interface module (sci). see serial communications interface module (sci) on page 163, serial peripheral interface module (spi) on page 197, timer interface module a (tima) on page 231 and i/o ports on page 307. port f i/o pins (ptf6eptf0/tach2) port f is a 7-bit special function port that shares four of its pins with the timer interface modules. see timer interface module a (tima) on page 231, timer interface module b (timb) on page 257 and i/o ports on page 307. 8-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC08AZ32 motorola general description 17 port g i/o pins (ptg2/kbd2eptg0 /kbd0) ptg2/kbd2 ptg0/kbd0 are general-purpose bidirectional i/o pins with key wakeup feature. see keyboard module (kb) on page 299 and i/o ports on page 307. port h i/o pins (pth1/kbd4epth0/ kbd3) pth1/kbd4 pth0/kbd3 are general-purpose bidirectional i/o pins with key wakeup feature. see keyboard module (kb) on page 299 and i/o ports on page 307. can transmit pin (cantx) cantx is the digital output from the mscan module. see mscan08 controller (mscan08) on page 331. can receive pin (canrx) canrx is the digital input to the mscan module. see mscan08 controller (mscan08) on page 373 9-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 18 general description motorola table 1. external pins summary pin name function driver type hysteresis reset state pta7 - pta0 general purpose i/o dual state no input (hi-z) ptb7/atd7 - ptb0/atd0 general purpose i/0 / adc channel dual state no input (hi-z) ptc5 - ptc0 general purpose i/o dual state no input (hi-z) ptd7 general purpose i/o dual state no input (hi-z) ptd6/atd14/taclk general purpose i/o / timer external input clock dual state no input (hi-z) ptd5/atd13 general purpose i/o/ timer external input clock dual state no input (hi-z) ptd4/atd12/tblck-p td0/atd8 general purpose input dual state no input (hi-z) pte7/spsck general purpose i/0 / spi clock dual state (open drain) yes input (hi-z) pte6/mosi general purpose i/0 / spi data path dual state (open drain) yes input (hi-z) pte5/miso general purpose i/0 / spi data path dual state (open drain) yes input (hi-z) pte4/ss general purpose i/0 / spi slave select dual state yes input (hi-z) pte3/tach1 general purpose i/0 / timer a channel 1 dual state yes input (hi-z) pte2/tach0 general purpose i/0 / timera channel 0 dual state yes input (hi-z) pte1/rxd general purpose i/0 / sci receive data dual state yes input (hi-z) pte0/txd general purpose i/0 / sci transmit data dual state yes input (hi-z) ptf6 general purpose i/o dual state yes input (hi-z) ptf5/tbch1 general purpose i/o /timer b channel 1 dual state yes input (hi-z) ptf4/tbch0 general purpose i/0 / timerb channel 0 dual state yes input (hi-z) 10-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC08AZ32 motorola general description 19 details of the clock connections to each of the modules on the MC68HC08AZ32 are shown in table 3 . a short description of each clock source is also given in table 2 . ptf3 general purpose i/0 dual state yes input (hi-z) ptf2 general purpose i/0 dual state yes input (hi-z) ptf1/tach3 general purpose i/0 /timera channel 3 dual state yes input (hi-z) ptf0/tach2 general purpose i/0 /timera channel 2 dual state yes input (hi-z) ptg2/kbd2 - ptg0/kbd0 general purpose i/0 with key wakeup feature dual state yes input (hi-z) pth1/kbd4- pth0/kbd3 general purpose i/0 with key wakeup feature dual state yes input (hi-z) v dd logical chip power supply na na na v ss logical chip ground na na na v dda analog power supply(cgm) na na na v ssa analog ground (cgm) na na na v refh adc reference voltage na na na a vss /vrefl adc gnd & reference voltage na na na v ddaref adc power supply na na na osc1 external clock in na na input (hi-z) osc2 external clock out na na output cgmxfc pll loop ?ter cap na na na irq external interrupt request na na input (hi-z) rst reset na na input (hi-z) canrx mscan serial input na yes input (hi-z) cantx mscan serial output output na output table 1. external pins summary (continued) pin name function driver type hysteresis reset state 11-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 20 general description motorola table 2. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmout pll-based or osc1-based clock output from cgm module) bus clock cgmout divided by two spsck spi serial clock (see spsck (serial clock) on page 221 ) taclk external clock input for tima (see tima clock pin (ptd6/taclk) on page 245 ) tbclk external clock input for timb (see timb clock pin (ptd4/tblck) on page 269 ) table 3. clock source summary module clock source adc cgmxclk or bus clock mscan cgmxclk or cgmout cop cgmxclk cpu bus clock eeprom cgmxclk or bus clock rom bus clock ram bus clock spi spsck sci cgmxclk tima bus clock or ptd6/atd14/taclk timb bus clock or ptd4/atd12/tblck pit bus clock kbi bus clock 12-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description ordering information MC68HC08AZ32 motorola general description 21 13-gen ordering information this section contains instructions for ordering the MC68HC08AZ32. mc order numbers table 4. mc order numbers mc order number operating temperature range MC68HC08AZ32cfu ?40 c to + 85 c MC68HC08AZ32vfu ?40 c to + 105 c MC68HC08AZ32mfu ?40 ? to + 125 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description MC68HC08AZ32 22 general description motorola 14-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola memory map 23 memory map memory map contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 introduction the cpu08 can address 64k bytes of memory space. the memory map includes: 1024 bytes of ram 32,272 bytes of user rom 512 bytes of eeprom 48 bytes of user-defined vectors 224 bytes of monitor rom the following definitions apply to the memory map representation of reserved and unimplemented locations. reserved ?accessing a reserved location can have unpredictable effects on mcu operation. unimplemented ?accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled. 1-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 24 memory map motorola i/o section addresses $0000?004f, shown in figure 2 , contain most of the control, status, and data registers. additional i/o registers have the following addresses: $0500 to $057f ?can control and message buffers. see mscan08 controller (mscan08) on page 331. $fe00 ?(sim break status register, sbsr) $fe01 ?(sim reset status register, srsr) $fe03 ?(sim break flag control register, sbfcr) $fe07 ?(eprom control register, epmcr) $fe0c and $fe0d ?(break address registers, brkh and brkl) $fe0e ?(break status and control register, brkscr) $fe0f ?(lvi status register, lvisr) $fe1c ?(eeprom non-volatile register, eenvr) $fe1d ?(eeprom control register, eecr) $fe1f ?(eeprom array configuration register, eeacr) $ffff ?(cop control register, copctl) 2-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section MC68HC08AZ32 motorola memory map 25 $0000 i/o registers (80 bytes) $004f $0050 ram (1024 bytes) $044f $0450 unimplemented (176 bytes) $04ff $0500 can control and message buffers(128 bytes) $057f $0580 unimplemented (640 bytes) $07ff $0800 eeprom (512 bytes) $09ff $0a00 unimplemented (1536 bytes) $0fff $1000 unimplemented ( 28,672 bytes) $7fff $8000 rom (16,384bytes) $bfff $c000 rom (15,872 bytes) $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved figure 1. MC68HC08AZ32 memory map 3-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 26 memory map motorola $fe06 unimplemented $fe07 reserved $fe08 reserved $fe09 reserved $fe0a reserved $fe0b unimplemented $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 unimplemented (12 bytes) $fe1b $fe1c eeprom non-volatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array configuration (eeacr) $fe20 monitor rom (224 bytes) $feff $ff00 unimplemented (192 bytes) $ffbf $ffc0 rom (16 bytes) $ffcf $ffd0 vectors (48 bytes) $ffff figure 1. MC68HC08AZ32 memory map (continued) 4-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section MC68HC08AZ32 motorola memory map 27 addr. name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) r: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 w: $0001 port b data register (ptb) r: ptb7 ptb6 ptb25 ptb4 ptb3 ptb2 ptb1 ptb0 w: $0002 port c data register r: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 w: $0003 port d data register (ptd) r: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 w: $0004 data direction register a (ddra) r: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w: $0005 data direction registerb (ddrb) r: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w: $0006 data direction register c (ddrc) r: mclke n 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w: $0007 data direction register d (ddrd) r: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 w: $0008 port e data register (pte) r: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 w: $0009 port f data register (ptf) r: 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 w: $000a port g data register (ptg) r: 0 0 0 0 0 ptg2 ptg1 ptg0 w: $000b port h data register (pth) r: 0 0 0 0 0 0 pth1 pth0 w: $000c data direction register e (ddre) r: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 w: $000d data direction register f (ddrf) r: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 w: $000e data direction register g (ddrg) r: 0 0 0 0 0 ddrg2 ddrg1 ddrg0 w: $000f data direction register (ddrh) r: 0 0 0 0 0 0 ddrh1 ddrh0 w: $0010 spi control register (spcr) r: sprie r sp- mstr cpol cpha spwom spe sptie w: $0011 spi status and control register (spscr) r: sprf 0 ovrf modf spte 0 spr1 spr0 w: $0012 spi data register (spdr) r: bit 7 6 5 4 3 2 1 bit 0 w: $0013 sci control register 1 (scc1) r: loops ensci txinv m wake ilty pen pty w: $0014 sci control register 2 (scc2) r: sctie tcie scrie ilie te re rwu sbk w: $0015 sci control register 3 (scc3) r: r8 t8 r r orie neie feie peie w: $0016 sci status register 1 (scs1) r: scte tc scrf idle or nf fe pe w: = unimplemented r = reserved figure 2. control, status, and data registers (sheet 1 of 5) 5-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 28 memory map motorola $0017 sci status register 2 (scs2) r: 0 0 0 0 0 0 bkf rpf w: $0018 sci data register (scdr) r: bit 7 6 5 4 3 2 1 bit 0 w: $0019 sci baud rate register (scbr) r: 0 0 scp1 scp0 0 scr2 scr1 scr0 w: $001a irq status and control register (iscr) r: irqf 0 imask1 mode1 w: ack1 $001b keyboard status/control (kbscr) r: 0 0 0 0 keyf 0 imaskk modek w: ackk $001c pll control register (pctl) r: pllie pllf pllon bcs 1111 w: $001d pll bandwidth control register (pbwc) r: auto lock acq xld 0000 w: $001e pll programming register (ppg) r: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 w: $001f mask option register a (mora) r: lvistop romsec lvirstd lvipwrd ssrec coprs stop copd w: r r r r r r r r $0020 timer a status and control register (tasc) r: tof toie tstop 00 ps2 ps1 ps0 w: 0 trst $0021 keyboard interrupt enable register (kbier) r; kbie4 kbie3 kbie2 kbie1 kbie0 w: $0022 timer a counter register high (tacnth) r: bit 15 14 13 12 11 10 9 bit 8 w; ?023 timer a counter register low (tacntl) r: bit 7 6 5 4 3 2 1 bit 0 w: $0024 timera modulo register high (tamodh) r: bit 15 14 13 12 11 10 9 bit 8 w: $0025 timera modulo register low (tamodl) r: bit 7 6 5 4 3 2 1 bit 0 w: $0026 timer a channel 0 status and control register (tasc0) r: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max w: 0 $0027 timera channel 0 register high (tach0h) r: bit 15 14 13 12 11 10 9 bit 8 w: $0028 timer a channel 0 register low (tach0l) r: bit 7 6 5 4 3 2 1 bit 0 w: $0029 timer a channel 1 status and control register (tasc1) r: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max w: 0 $002a timer a channel 1 register high (tach1h) r: bit 15 14 13 12 11 10 9 bit 8 w: $002b timer a channel 1 register low (tach1l) r: bit 7 6 5 4 3 2 1 bit 0 w: $002c timer a channel 2 status and control register (tasc2) r: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max w: 0 addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved figure 2. control, status, and data registers (sheet 2 of 5) 6-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section MC68HC08AZ32 motorola memory map 29 $002d timer a channel 2 register high (tach2h) r: bit 15 14 13 12 11 10 9 bit 8 w: $002e timer a channel 2 register low (tach2l) r: bit 7 6 5 4 3 2 1 bit 0 w: $002f timer channel 3 status and control register (tasc3) r: ch3f ch3ie ms3b ms3a els3b els3a tov3 ch3max w: 0 $0030 timer channel 3 register high (tach3h) r: bit 15 14 13 12 11 10 9 bit 8 w: $0031 timer channel 3 register low (tach3l) r: bit 7 6 5 4 3 2 1 bit 0 w: $0032 unimplemented r: w: $0033 unimplemented r: w: $0034 unimplemented r: w: $0035 unimplemented r: w: $0036 unimplemented r: w: $0037 unimplemented r: w: $0038 adscr r: coco aien adco ch4 ch3 ch2 ch1 ch0 w: r $0039 adr r: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w: $003a adc input clock select (adclkr) r: adiv2 adiv1 adiv0 adiclk 0000 w: $003b reserved r: rr r r rrrr w: $003c reserved r: rr r r rrrr w: $003d unimplemented r: w: $003e unimplemented r: w: $003f mask option register b (morb) r: rr eesec rrrrr w: $0040 timerb status and control register (tbsc) r: tof toie tstop 00 ps2 ps1 ps0 w: 0 trst $0041 timerb counter register high (tbcnth) r: bit 15 14 13 12 11 10 9 8 w: addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved figure 2. control, status, and data registers (sheet 3 of 5) 7-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 30 memory map motorola $0042 timerb counter register low (tbcntl) r: bit 7 6 5 4 3 2 1 0 w: $0043 timerb modulo register high (tbmodh) r: bit 15 14 13 12 11 10 9 bit 8 w: $0044 timerb modulo register low (tbmodl) r: bit 7 6 5 4 3 2 1 bit 0 w: $0045 timer b channel 0status and control register (tbsc0) r: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch0max w: 0 $0046 timer b channel 0register high (tbch0h) r: bit 15 14 13 12 11 10 9 8 w: $0047 timer b channel 0register low (tbch0l) r: bit 7 6 5 4 3 2 1 0 w: $0048 timer b channel 1status/ control register (tbsc1) r: ch5f ch5ie ms5b ms5a els5b els5a tov5 ch1max w: 0 $0049 timer b channel 1register high (tbch1h) r: bit 15 14 13 12 11 10 9 8 w: $004a timer b channel1register low (tbch1l) r: bit 7 6 5 4 3 2 1 0 w: $004b programmable interrupt timer status & control register (psc) r: pof pie pstop 0 0 pps2 pps1 pps0 w: 0 prst $004c pit counter register high) (pcnth) r: bit 15 14 13 12 11 10 9 8 w: $004d pit counter register low (pcntl) r: 7 6 5 4 3 2 1 0 w $004e pit modulo register high (pmodh) r bit 15 14 13 12 11 10 9 8 w $004f pit modulo register low (pmodl) r: 7 6 5 4 3 2 1 0 w $fe00 sim break status register (sbsr) r: r r r r r r sbsw r w: $fe01 sim reset status register (srsr) r: por pin cop ilop ilad 0 lvi 0 w: $fe03 sim break flag control register (sbfcr) r: bcfe r r r r r r r w: $fe07 reserved r: w: $fe0c break address register high (brkh) r: bit 15 14 13 12 11 10 9 bit 8 w: $fe0d break address register low (brkl) r: bit 7 6 5 4 3 2 1 bit 0 w: addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved figure 2. control, status, and data registers (sheet 4 of 5) 8-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section MC68HC08AZ32 motorola memory map 31 $fe0e break status and control register (brkscr) r: brke brka 000000 w: $fe0f lvi status register (lvisr) r: lviout 00 000 0 0 w: $fe1c eenvr r: eera con2 con1 con0 eepb3 eepb2 eepb1 eepb0 w: $fe1d eecr r: eebclk 0 eeoff eeras1 eeras0 elat 0 eepgm w: $fe1e reserved r: rr r r rrrr w: $fe1f eeacr r: eera con2 con1 con0 eebp3 eebp2 eebp1 eebp0 w: $ffff cop control register (copctl) r: low byte of reset vector w: writing to $ffff clears cop counter addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved figure 2. control, status, and data registers (sheet 5 of 5) 9-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 32 memory map motorola table 1. vector addresses (1) address vector low $ffd0 adc vector (high) $ffd1 adc vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda mscan transmit vector(high) $ffdb mscan transmit vector (low) $ffdc mscan receive vector(high) $ffdd mscan receive vector (low) $ffde mscan error vector(high) $ffdf mscan error vector (low) $ffe0 mscan wakeup vector(high) $ffe1 mscan wakeup vector (low) $ffe2 spi transmit vector(high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector(high) $ffe5 spi receive vector (low) $ffe6 timb overflow vector(high) $ffe7 timb overflow vector (low) $ffe8 timb ch1 vector(high) $ffe9 timb ch1 vector (low) $ffea timb ch0 vector(high) $ffeb timb ch0 vector (low) $ffec tima overflow vector(high) $ffed tima overflow vector (low) $ffee tima ch3 vector(high) $ffef tima ch3 vector (low) $fff0 timach2 vector(high) $fff1 tima ch2 vector (low) $fff2 tima ch1 vector(high) $fff3 tima ch1 vector (low) $fff4 tima ch0 vector(high) $fff5 tima ch0 vector (low) $fff6 pit vector(high) $fff7 pit vector (low) $fff8 pll vector(high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector(high) $fffd swi vector (low) $fffe reset vector (high) high $ffff reset vector (low) priority 10-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section MC68HC08AZ32 motorola memory map 33 11-mem 1. all available rom locations not defined by the user will by default be filled with the software interrupt (swi, opcode 83) instruction ?see central processor unit (cpu) . take this into account when defining vector addresses. it is recommended that all vector addresses are defined. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC08AZ32 34 memory map motorola 12-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola ram 35 ram ram contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 introduction this section describes the 1024 bytes of ram. functional description addresses $0050 through $044f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero there are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can efficiently access all page zero ram locations. page zero ram, therefore, provides an ideal location for frequently accessed global variables. before processing an interrupt, the cpu uses 5 bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. 1-ram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ram MC68HC08AZ32 36 ram motorola during a subroutine call, the cpu uses 2 bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: care should be taken when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2-ram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola rom 37 rom rom contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 introduction this section describes the operation of the embedded rom memory. functional description the user rom consists of up to 32, 272 bytes from addresses $8000?fdff and $ffc0?ffcf. the monitor rom and vectors are located from $fe20?feff. forty-eight user vectors, $ffd0?ffff, are dedicated to user-defined reset and interrupt vectors. security security has been incorporated into the MC68HC08AZ32 to prevent external viewing of the rom contents 1 . this feature is selected by a mask option and ensures that customer-developed software remains propriety. see mask options on page 119. 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the rom difficult for unauthorized users. 1-rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . rom MC68HC08AZ32 38 rom motorola 2-rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola eeprom 39 eeprom eeprom contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 future eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 eeprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 eeprom configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mcu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MC68HC08AZ32 eeprom security . . . . . . . . . . . . . . . . . . . . . . . 45 eeprom control register (eecr) . . . . . . . . . . . . . . . . . . . . . . . . . 46 eeprom non-volatile register (eenvr) and eeprom array configuration register (eeacr) . . . . . . . . . . . . . . . . . . . . . . . 48 low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 40 eeprom motorola introduction this section describes the electrically erasable programmable rom (eeprom). future eeprom memory design is underway to introduce an improved eeprom module, which will simplify programming and erase. current read, write and erase algorithms are fully compatible with the new eeprom design. the new eeprom module requires a constant timebase through the set up of new timebase control registers. if more information is required for code compatibility please contact the factory. the silicon differences will be identified by mask set. please read appendix c: future eeprom registers for preliminary details. note: this new silicon will not allow multiple writes before erase. eeprom bytes must be erased before reprogramming. features byte, block or bulk erasable non-volatile block protection option non-volatile mcu configuration bits on-chip charge pump for programming/erasing. 2-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC08AZ32 motorola eeprom 41 functional description 512 bytes of eeprom can be programmed or erased without an external voltage supply. the eeprom has a lifetime of 10,000 write-erase cycles. eeprom cells are protected with a non-volatile block protection option. these options are stored in the eeprom non-volatile register (eenvr) and are loaded into the eeprom array configuration register after reset (eeacr) or after a read of eenvr. hardware interlocks are provided to protect stored data corruption from accidental programming/erasing. the eeprom array will leave the factory in the erased state all addresses logic ?? and bit 4 of the eenvr register will be programmed to #1 such that the full array is available and unprotected. eeprom programming the unprogrammed state is a logic ?? programming changes the state to a logic ?? only valid eeprom bytes in the non-protected blocks and eenvr can be programmed. it is recommended that all bits should be erased before being programmed. the following procedure describes how to program a byte of eeprom: 1. clear eeras1 and eeras0 and set eelat in the eecr (see note a. and b. ) 2. write the desired data to any user eeprom address. 3. set the eepgm bit. (see note c. ) 4. wait for a time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for the programming voltage time to fall (t eefpv ). 7. clear eelat bits. (see note d. ) 8. repeat steps 1 to 7 for more eeprom programming. 3-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 42 eeprom motorola notes: a. eeras1 and eeras0 must be cleared for programming, otherwise the part will be in erase mode b. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom address will be latched. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. any attempts to read other eeprom data will result in the latched data being read. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. c. the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. this is to ensure proper programming sequence. when eepgm is set, the on-board charge pump generates the program voltage and applies it to the user eeprom array. when the eepgm bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off. d. any attempt to clear both eepgm and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. e. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. eeprom erasing the unprogrammed state is a logic ?? only the valid eeprom bytes in the non-protected blocks and eenvr can be erased. the following procedure shows how to erase eeprom: 1. clear/set eeras1 and eeras0 to select byte/block/bulk erase, and set eelat in eecr (see note f. ) 2. write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. set the eepgm bit. (see note g. ) 4. wait for a time, t byte /t block /t bulk before erasing the 4-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC08AZ32 motorola eeprom 43 byte/block/array. 5. clear eepgm bit. 6. wait for the erasing voltage time to fall (t eefpv ). 7. clear eelat bits. (see note h. ) 8. repeat steps 1 to 7 for more eeprom byte/block erasing. the eebpx bit must be cleared to erase eeprom data in the corresponding block. if any eebpx is set, the corresponding block cannot be erased and bulk erase mode does not apply. notes: f. setting the eelat bit configures the address and data buses to latch data for erasing the array. only valid eeprom addresses with its data will be latched. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. in block erase mode, any eeprom address in the block may be used in step 2. all locations within this block will be erased. in bulk erase mode, any eeprom address may be used to erase the whole eeprom. eenvr is not affected with block or bulk erase. any attempts to read other eeprom data will result in the latched data being read. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. g. the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. this is to ensure proper erasing sequence. once eepgm is set, the type of erase mode cannot be modified. if eepgm is set, the on-board charge pump generates the erase voltage and applies it to the user eeprom array. when the eepgm bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. h. any attempt to clear both eepgm and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. in general, all bits should be erased before being programmed. 5-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 44 eeprom motorola eeprom block protection the 512 bytes of eeprom is divided into four 128 byte blocks. each of these blocks can be separately protected by the eebpx bit. any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. table 2 shows the address ranges within the blocks. if the eebpx bit is set, the corresponding address block is protected. these bits are effective after a reset or a read to eenvr register. the block protect configuration can be modified by erasing/programming the corresponding bits in the eenvr register and then reading the eenvr register. eeprom configuration the eeprom non-volatile register (eenvr) contains configurations concerning block protection and redundancy. eenvr is physically located on the bottom of the eeprom array. the contents are non-volatile and are not modified by reset. on reset, this special register loads the eeprom configuration into a corresponding volatile eeprom array configuration register (eeacr). thereafter, all reads to the eenvr will result in eeacr being reloaded. the eeprom configuration can be changed by programming/erasing the eenvr like a normal eeprom byte. the new array configuration will take effect with a system reset or a read of the eenvr. mcu configuration the eeprom non-volatile register (eenvr) also contains general purpose bits which can be used to enable/disable functions within the mcu which, for safety reasons, need to be controlled from non-volatile table 2. eeprom array address blocks block number (eebpx) address range eebp0 $0800?087f eebp1 $0880?08ff eebp2 $0900?097f eebp3 $0980?09ff 6-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC08AZ32 motorola eeprom 45 memory. on reset, this special register loads the mcu configuration into the volatile eeprom array configuration register (eeacr). thereafter, all reads to the eenvr will result in eeacr being reloaded. the mcu configuration can be changed by programming/erasing the eenvr like a normal eeprom byte. please note that it is the users responsibility to program the eenvr register to the correct system requirements and verify it prior to use. the new array configuration will take effect with a system reset or a read of the eenvr. MC68HC08AZ32 eeprom security the MC68HC08AZ32 has a special security option which prevents program/erase access to memory locations $08f0 to $08ff. this security function is enabled by programming the con0 bit in the eenvr to 0. in addition to disabling the program and erase operations on memory locations $08f0 to $08ff the enabling of the security option has the following effects: bulk and block erase modes are disabled. programming and erasing of the eenvr is disabled. non secure locations ($0800?08ef) can be erased using the single byte erase function as normal. secured locations can be read as normal. writing to a secured location no longer qualifies as a ?alid eeprom write?as detailed in eeprom programming note a. , and eeprom erasing note f. note: once armed, the security is permanently enabled. as a consequence, all functions in the eenvr will remain in the state they were in immediately before the security was enabled. 7-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 46 eeprom motorola eeprom control register (eecr) this read/write register controls programming/erasing of the array. eebclk ?eeprom bus clock enable this read/write bit determines which clock will be used to drive the internal charge pump for programming/erasing. reset clears this bit. 1 = bus clock drives charge pump 0 = internal rc oscillator drives charge pump note: it is recommended that the internal rc oscillator is used to drive the internal charge pump for applications which have a bus frequency of less than 8mhz. eeoff ?eeprom power down this read/write bit disables the eeprom module for lower power consumption. any attempts to access the array will give unpredictable results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array note: the eeprom requires a recovery time t eeoff to stabilize after clearing the eeoff bit. 76543210 eecr $fe1d read: eebclk 0 eeoff eeras1 eeras0 eelat 0 eepgm write: reset: 00000000 = unimplemented figure 1. eeprom control register (eecr) 8-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC08AZ32 motorola eeprom 47 eeras1?eras0 ?erase bits these read/write bits set the erase modes. reset clears these bits. eelat ?eeprom latch control this read/write bit latches the address and data buses for programming the eeprom array. eelat can not be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom programming 0 = buses configured for normal read operation eepgm ?eeprom program/erase enable this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom array if the eelat bit is set and a write to a valid eeprom location has occurred. reset clears the eepgm bit. 1 = eeprom programming/erasing power switched on 0 = eeprom programming/erasing power switched off note: writing ?? to both the eelat and eepgm bits with a single instruction will only clear eepgm. this is to allow time for the removal of high voltage. table 3. eeprom program/erase mode select eebpx eeras1 eera0 mode 0 0 0 byte program 0 0 1 byte erase 0 1 0 block erase 0 1 1 bulk erase 1 x x no erase/program x = don? care 9-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 48 eeprom motorola eeprom non-volatile register (eenvr) and eeprom array configuration register (eeacr) eera ?eeprom redundant array this bit is reserved for future use and should always be equal to 0. conx ?mcu configuration bits these read/write bits can be used to enable/disable functions within the mcu. reset loads conx from eenvr to eeacr. con2 ?unused con1 ?unused con0 ?eeprom security 1 = eeprom security disabled 0 = eeprom security enabled eebp3?ebp0 ?eeprom block protection bits. these read/write bits prevent blocks of eeprom array from being programmed or erased. reset loads eebp[3:0] from eenvr to eeacr. 1 = eeprom array block is protected 0 = eeprom array block is unprotected 76543210 eenvr $fe1c read: eera con2 con1 con0 eebp3 eebp2 eebp1 eebp0 write: reset: pv pv pv pv pv pv pv pv pv = programmed value or ??in the erased state. figure 2. eeprom non-volatile register (eenvr) 76543210 eeacr $fe1f read: eera con2 con1 con0 eebp3 eebp2 eebp1 eebp0 write: reset: eenvr eenvr eenvr eenvr eenvr eenvr eenvr eenvr = unimplemented figure 3. eeprom array control register (eeacr) 10-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC08AZ32 motorola eeprom 49 low power modes the wait and stop instructions can put the mcu in low power consumption standby modes. wait mode the wait instruction does not affect the eeprom. it is possible to program the eeprom and put the mcu in wait mode. however, if the eeprom is inactive, power can be reduced by setting the eeoff bit before executing the wait instruction. stop mode the stop instruction reduces the eeprom power consumption to a minimum. the stop instruction should not be executed while the high voltage is turned on (eepgm=1). if stop mode is entered while program/erase is in progress, high voltage will automatically be turned off. however, the eepgm bit will remain set. when stop mode is terminated, if eepgm is still set, the high voltage will automatically be turned back on. program/erase time will need to be extended if program/erase is interrupted by entering stop mode. the module requires a recovery time t eestop to stabilize after leaving stop mode. attempts to access the array during the recovery time will result in unpredictable behavior. 11-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom MC68HC08AZ32 50 eeprom motorola 12-eeprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola central processor unit (cpu) 51 central processor unit (cpu) central processor unit (cpu) contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 stack pointer (sp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 program counter (pc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 arithmetic/logic unit (alu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 introduction this section describes the central processor unit (cpu8). the m68hc08 cpu is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 1-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 52 central processor unit (cpu) motorola features features of the cpu include the following: full upward, object-code compatibility with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8.4mhz cpu internal bus frequency 64k byte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling low-power stop and wait modes 2-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC08AZ32 motorola central processor unit (cpu) 53 cpu registers figure 1 shows the five cpu registers. cpu registers are not part of the memory map. figure 1. cpu registers accumulator (a) the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two? complement overflow flag v1 1h i nzc h x 0 0 0 0 7 15 15 15 70 bit 7 654321 bit 0 a read: write: reset: unaffected by reset figure 1. accumulator (a) 3-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 54 central processor unit (cpu) motorola index register (h:x) the 16-bit index register allows indexed addressing of a 64k byte memory space. h is the upper byte of the index register and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can also be used as a temporary data storage location. stack pointer (sp) the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 151413121110987654321 bit 0 h:x read: write: reset: 00000000 xxxxxxxx x = indeterminate figure 1. index register (h:x) bit 151413121110987654321 bit 0 sp read: write: reset: 0000000011111111 figure 1. stack pointer (sp) 4-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC08AZ32 motorola central processor unit (cpu) 55 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page zero ($0000 to $00ff) frees direct address (page zero) space. for correct operation, the stack pointer must point only to ram locations. program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. condition code register (ccr) the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to ?? the following paragraphs describe the functions of the condition code register. bit 151413121110987654321 bit 0 pc read: write: reset: loaded with vector from $fffe and $ffff figure 1. program counter (pc) bit 7 654321 bit 0 ccr read: v1 1h i nzc write: reset: x 1 1x1xxx x = indeterminate figure 1. condition code register (ccr) 5-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 56 central processor unit (cpu) motorola v ?overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ?half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ?interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return from interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (cli). 6-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) arithmetic/logic unit (alu) MC68HC08AZ32 motorola central processor unit (cpu) 57 n ?negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ?zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ?carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about cpu architecture. 7-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 58 central processor unit (cpu) motorola cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. see break module on page 123. the program counter vectors to $fffc?fffd ($fefc?fefd in monitor mode). a return from interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. instruction set summary table 1 provides a summary of the m68hc08 instruction set. 8-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary MC68HC08AZ32 motorola central processor unit (cpu) 59 table 1 instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? (sp) + (16 m) imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? (h:x) + (16 m) imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ? (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c 9-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 60 central processor unit (cpu) motorola bclr n , opr clear bit n in m mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? (z) = 1 rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 0 rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 0 rel 92 rr 3 bhcc rel branch if half carry bit clear pc ? (pc) + 2 + rel ? (h) = 0 rel 28 rr 3 bhcs rel branch if half carry bit set pc ? (pc) + 2 + rel ? (h) = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? (c) | (z) = 0 rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 1rel 93 rr 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? (c) | (z) = 1 rel 23 rr 3 blt opr branch if less than (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 1 rel 91 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? (i) = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? (n) = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? (i) = 1 rel 2d rr 3 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 10-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary MC68HC08AZ32 motorola central processor unit (cpu) 61 bne rel branch if not equal pc ? (pc) + 2 + rel ? (z) = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? (n) = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc ? (pc) + 3 + rel ? (mn) = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ? (pc) + 3 + rel ? (mn) = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (x) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 2 + rel ? (a) ?(m) = $00 pc ? (pc) + 4 + rel ? (a) ?(m) = $00 dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ? 0 ?inh 98 1 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ? $00 a ? $00 x ? $00 h ? $00 m ? $00 m ? $00 m ? $00 001 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 11-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 62 central processor unit (cpu) motorola cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one s complement) m ? (m ) = $ff ?(m) a ? (a ) = $ff ?(m) x ? (x ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) 0 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ?(m:m + 1) imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a ? (a) ?1 or m ? (m) ?1 or x ? (x) ?1 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 4 + rel ? (result) 1 0 dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ? (h:a)/(x) h ? remainder inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? (a ? m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 12-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary MC68HC08AZ32 motorola central processor unit (cpu) 63 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n ( n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ? ( m:m + 1 ) 0 imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right 0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? (m) source h:x ? (h:x) + 1 (ix+d, dix+) 0 dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? (x) (a) ??inh 42 5 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 13-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 64 central processor unit (cpu) motorola neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two s complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none inh 9d 1 nsa nibble swap a a ? (a[3:0]:a[7:4]) inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ? (a) | (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? (sp ) 1 inh 87 2 pshh push h onto stack push (h) ; sp ? (sp ) ? 1 inh 8b 2 pshx push x onto stack push (x) ; sp ? (sp ) ? 1 inh 89 2 pula pull a from stack sp ? (sp + 1); pull ( a ) inh 86 2 pulh pull h from stack sp ? (sp + 1); pull ( h ) inh 8a 2 pulx pull x from stack sp ? (sp + 1); pull ( x ) inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp ? $ff inh 9c 1 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp ? sp + 1 ; pull ( pch) sp ? sp + 1; pull (pcl) inh 81 4 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c 14-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary MC68HC08AZ32 motorola central processor unit (cpu) 65 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? 1 ?inh 99 1 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ? (a) 0 dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? (h:x) 0 dir 35 dd 4 stop enable irq pin; stop oscillator i ? 0; stop oscillator 0 inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ? (x) 0 dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (a) (m) imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 9 tap transfer a to ccr ccr ? (a) inh 84 2 tax transfer a to x x ? (a) inh 97 1 tpa transfer ccr to a a ? (ccr) inh 85 1 table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 15-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 66 central processor unit (cpu) motorola opcode map tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ?$00 or (x) ?$00 or (m) ?$00 0 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ? (sp) + 1 inh 95 2 txa transfer x to a a ? (x) inh 9f 1 txs transfer h:x to sp (sp) ? (h:x) ?1 inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccrcondition code registerpc program counter dddirect address of operandpch program counter high byte dd rrdirect address of operand and relative offset of branch instructionpcl program counter low byte dddirect to direct addressing moderel relative addressing mode dirdirect addressing mode rel relative program counter offset byte dix+direct to indexed with post increment addressing moderr relative program counter offset byte ee ffhigh and low bytes of offset in indexed, 16-bit offset addressingsp1 stack pointer, 8-bit offset addressing mode extextended addressing modesp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressingsp stack pointer h half-carry bitu unde?ed h index register high bytev over?w bit hh llhigh and low bytes of operand address in extended addressingx index register low byte i interrupt maskz zero bit ii immediate operand byte& logical and imdimmediate source to direct destination addressing mode| logical or immimmediate addressing mode ? logical exclusive or inhinherent addressing mode( ) contents of ixindexed, no offset addressing mode? ) negation (two s complement) ix+indexed, no offset, post increment addressing mode# immediate value ix+dindexed with post increment to direct addressing mode sign extend ix1indexed, 8-bit offset addressing mode ? loaded with ix1+indexed, 8-bit offset, post increment addressing mode? if ix2indexed, 16-bit offset addressing mode: concatenated with mmemory location set or cleared n negative bit not affected table 1 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 16-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola central processor unit (cpu) 67 central processor unit (cpu) opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3 dir 4 bset0 2 dir 3 bra 2 rel 4 neg 2 dir 1 nega 1 inh 1 negx 1 inh 4 neg 2 ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1 inh 3 bge 2 rel 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 4 sub 3 ix2 5 sub 4 sp2 3 sub 2 ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3 dir 4 bclr0 2 dir 3 brn 2 rel 5 cbeq 3 dir 4 cbeqa 3 imm 4 cbeqx 3 imm 5 cbeq 3 ix1+ 6 cbeq 4 sp1 4 cbeq 2 ix+ 4 rts 1 inh 3 blt 2 rel 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 4 cmp 3 ix2 5 cmp 4 sp2 3 cmp 2 ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3 dir 4 bset1 2 dir 3 bhi 2 rel 5 mul 1 inh 7 div 1 inh 3 nsa 1 inh 2 daa 1 inh 3 bgt 2 rel 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 4 sbc 3 ix2 5 sbc 4 sp2 3 sbc 2 ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3 dir 4 bclr1 2 dir 3 bls 2 rel 4 com 2 dir 1 coma 1 inh 1 comx 1 inh 4 com 2 ix1 5 com 3 sp1 3 com 1ix 9 swi 1 inh 3 ble 2 rel 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 4 cpx 3 ix2 5 cpx 4 sp2 3 cpx 2 ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3 dir 4 bset2 2 dir 3 bcc 2 rel 4 lsr 2 dir 1 lsra 1 inh 1 lsrx 1 inh 4 lsr 2 ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1 inh 2 txs 1 inh 2 and 2 imm 3 and 2 dir 4 and 3 ext 4 and 3 ix2 5 and 4 sp2 3 and 2 ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3 dir 4 bclr2 2 dir 3 bcs 2 rel 4 sthx 2 dir 3 ldhx 3 imm 4 ldhx 2 dir 3 cphx 3 imm 4 cphx 2 dir 1 tpa 1 inh 2 tsx 1 inh 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 4 bit 3 ix2 5 bit 4 sp2 3 bit 2 ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3 dir 4 bset3 2 dir 3 bne 2 rel 4 ror 2 dir 1 rora 1 inh 1 rorx 1 inh 4 ror 2 ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1 inh 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 4 lda 3 ix2 5 lda 4 sp2 3 lda 2 ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3 dir 4 bclr3 2 dir 3 beq 2 rel 4 asr 2 dir 1 asra 1 inh 1 asrx 1 inh 4 asr 2 ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1 inh 1 ta x 1 inh 2 ais 2 imm 3 sta 2 dir 4 sta 3 ext 4 sta 3 ix2 5 sta 4 sp2 3 sta 2 ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3 dir 4 bset4 2 dir 3 bhcc 2 rel 4 lsl 2 dir 1 lsla 1 inh 1 lslx 1 inh 4 lsl 2 ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1 inh 1 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 4 eor 3 ix2 5 eor 4 sp2 3 eor 2 ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3 dir 4 bclr4 2 dir 3 bhcs 2 rel 4 rol 2 dir 1 rola 1 inh 1 rolx 1 inh 4 rol 2 ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1 inh 1 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 4 adc 3 ix2 5 adc 4 sp2 3 adc 2 ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3 dir 4 bset5 2 dir 3 bpl 2 rel 4 dec 2 dir 1 deca 1 inh 1 decx 1 inh 4 dec 2 ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1 inh 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 4 ora 3 ix2 5 ora 4 sp2 3 ora 2 ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3 dir 4 bclr5 2 dir 3 bmi 2 rel 5 dbnz 3 dir 3 dbnza 2 inh 3 dbnzx 2 inh 5 dbnz 3 ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1 inh 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 4 add 3 ix2 5 add 4 sp2 3 add 2 ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3 dir 4 bset6 2 dir 3 bmc 2 rel 4 inc 2 dir 1 inca 1 inh 1 incx 1 inh 4 inc 2 ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1 inh 1 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix d 5 brclr6 3 dir 4 bclr6 2 dir 3 bms 2 rel 3 tst 2 dir 1 tsta 1 inh 1 tstx 1 inh 3 tst 2 ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1 inh 4 bsr 2 rel 4 jsr 2 dir 5 jsr 3 ext 6 jsr 3 ix2 5 jsr 2 ix1 4 jsr 1ix e 5 brset7 3 dir 4 bset7 2 dir 3 bil 2 rel 5 mov 3dd 4 mov 2 dix+ 4 mov 3 imd 4 mov 2 ix+d 1 stop 1 inh * 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 4 ldx 3 ix2 5 ldx 4 sp2 3 ldx 2 ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3 dir 4 bclr7 2 dir 3 bih 2 rel 3 clr 2 dir 1 clra 1 inh 1 clrx 1 inh 3 clr 2 ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1 inh 1 txa 1 inh 2 aix 2 imm 3 stx 2 dir 4 stx 3 ext 4 stx 3 ix2 5 stx 4 sp2 3 stx 2 ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3 dir cycles opcode mnemonic number of bytes / addressing mode table 2: opcode map msb lsb msb lsb 17-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) MC68HC08AZ32 68 central processor unit (cpu) motorola 18-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola system integration module (sim) 69 system integration module (sim) sim contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . 72 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 clock start-up from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . 73 clocks in stop and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . 73 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 active resets from internal sources. . . . . . . . . . . . . . . . . . . . . . . . . 75 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . 77 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . 78 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 sim counter during power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . 79 sim counter during stop mode recovery . . . . . . . . . . . . . . . . . . . 79 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . 84 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 sim break status register (sbsr). . . . . . . . . . . . . . . . . . . . . . . . . . 88 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 89 sim break flag control register (sbfcr) . . . . . . . . . . . . . . . . . . . . 90 1-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 70 system integration module (sim) motorola introduction this section describes the system integration module, which supports up to 24 external and/or internal interrupts. together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 1 . table 1 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals stop/wait/reset/break entry and recovery internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: acknowledge timing arbitration control timing vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources 2-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction MC68HC08AZ32 motorola system integration module (sim) 71 figure 1. sim block diagram table 2 shows the internal signal names used in this section. table 1. sim i/o register summary register name bit 7 654321 bit 0 addr. sim break status register (sbsr) r rrrrr sbsw r $fe00 sim reset status register (srsr) por pin cop ilop ilad 0 lvi 0 $fe01 sim break flag control register (sbfcr) bcfe 0000000 $fe03 r = reserved for factory test stop/wait clock control por control reset pin control module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) ? 2 interrupt control and priority decode sim reset status register clock generators 3-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 72 system integration module (sim) motorola sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 2 . this clock can come from either an external oscillator or from the on-chip pll. see clock generator module (cgm) on page 91. figure 2. cgm clock signals table 2. signal naming conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal pll osc1 cgmxclk ? 2 sim cgm ptc3 clock select circuit cgmvclk bcs ? 2 a b s * cgmout * when s = 1, cgmout = b user mode sim counter bus clock generators monitor mode 4-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation MC68HC08AZ32 motorola system integration module (sim) 73 bus timing in user mode , the internal bus frequency is either the crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see clock generator module (cgm) on page 91. clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 cgmxclk cycle por timeout has been completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. clocks in stop and wait mode upon exit from stop mode (by an interrupt, break, or reset), the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. see stop mode on page 86. in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 5-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 74 system integration module (sim) motorola reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?fff ($fefe?eff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter, see sim counter on page 79, but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see sim registers on page 88. external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 3 for details. figure 3 shows the relative timing. table 3. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) 6-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC08AZ32 motorola system integration module (sim) 75 figure 3. external reset timing active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow for resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. see figure 4 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. see figure 5 . note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles, during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst as shown in figure 4 . figure 4. internal reset timing rst iab pc vect h vect l cgmout irst rst r s t pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk 7-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 76 system integration module (sim) motorola the cop reset is asynchronous to the bus clock. figure 5. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated the internal reset signal is asserted the sim enables cgmout internal clocks to the cpu and modules are held inactive for 4096 cgmxclk cycles to allow the oscillator to stabilize the rst pin is driven low during the oscillator stabilization time the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared illegal address rst illegal opcode rst coprst lvi por internal reset 8-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC08AZ32 motorola system integration module (sim) 77 figure 6. por recovery computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, a value (any value) should be written to location $ffff. writing to location $ffff clears the cop counter and bits 12 through 4 of the sim counter. the sim counter output, which occurs at least every 2 13 ?2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v dd + v hi while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v dd + v hi on the rst pin disables the cop module. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff 9-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 78 system integration module (sim) motorola illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic ?? the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. note: extra care should be exercised if code in this port has been taken from another hc08 with a different memory map since some legal addresses could become illegal addresses on a smaller rom. it is the user? responsibility to check their code for illegal addresses. low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 10-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter MC68HC08AZ32 motorola system integration module (sim) 79 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clocked by the falling edge of cgmxclk. sim counter during power-on reset the power-on reset (por) module detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. sim counter during stop mode recovery the sim counter is also used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a logic ?? then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. sim counter and reset states external reset has no effect on the sim counter. (see stop mode on page 86. for details). the sim counter is free-running after all reset states, see active resets from internal sources on page 75 for counter control and internal reset recovery sequences. 11-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 80 system integration module (sim) motorola exception control normal, sequential program execution can be changed in three different ways: interrupts maskable hardware cpu interrupts non-maskable software interrupt instruction (swi) reset break interrupts interrupts at the beginning of an interrupt, the cpu saves the cpu register contents onto the stack and sets the interrupt mask (i-bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 7 shows interrupt entry timing, and figure 9 shows interrupt recovery timing. figure 7 . interrupt entry interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt may take precedence, regardless of priority, module idb r/w interrupt dummy sp sp ?1 sp ?2 sp ?3 sp ?4 vect h vect l start address iab dummy pc ?1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i-bit 12-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC08AZ32 motorola system integration module (sim) 81 until the latched interrupt is serviced (or the i-bit is cleared). see figure 8 . figure 8. interrupt processing no no no yes no no yes yes (as many interrupts as exist on chip) i bit set? from reset i-bit set? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i-bit. load pc with interrupt vector. execute instruction. yes yes break interrupt? irq interrupt? 13-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 82 system integration module (sim) motorola figure 9. interrupt recovery hardware interrupts processing of a hardware interrupt begins after completion of the current instruction. when the instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i-bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 9 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i-bit) in the condition code register. module idb r/w interrupt sp ?4 sp ?3 sp ?2 sp ?1 sp pc pc + 1 iab ccr a x pc ?1[7:0] pc ? 1[15:8] opcode operand i-bit 14-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) break interrupts MC68HC08AZ32 motorola system integration module (sim) 83 note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ?1, as a hardware interrupt does. reset all reset sources always have equal and highest priority and cannot be arbitrated. break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. see break module on page 123. the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. figure 10. interrupt recognition example cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine 15-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 84 system integration module (sim) motorola status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ?for example, a read of one register followed by the read or write of another ?are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 16-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes MC68HC08AZ32 motorola system integration module (sim) 85 low-power modes executing the stop/wait instruction puts the mcu in a low-power-consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 11 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the mask option register is ?? then the computer operating properly (cop) module is enabled and remains active in wait mode. figure 11. wait mode entry timing figure 11 and figure 13 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. 17-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 86 system integration module (sim) motorola figure 13. wait recovery from internal reset stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the mask option register (mor). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. figure 12. wait recovery from interrupt or break $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles 18-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes MC68HC08AZ32 motorola system integration module (sim) 87 note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 14 shows stop mode entry timing. figure 14. stop mode entry timing figure 15. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ?1 sp ?2 sp ?3 stop +1 stop recovery period 19-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 88 system integration module (sim) motorola sim registers the sim has three memory mapped registers. table 4 shows the mapping of these registers. sim break status register (sbsr) the sim break status register contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ?sim break stop/wait this status bit is useful in applications requiring a return to stop or wait mode after exiting from a break interrupt. sbsw can be cleared by writing a logic ??to it. reset clears sbsw. 1 = stop or wait mode was exited by break interrupt 0 = stop or wait mode was not exited by break interrupt table 4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user bit 7 654321 bit 0 sbsr $fe00 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved for factory test 1. writing a logic ? clears sbsw. figure 16. sim break status register (sbsr) 20-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers MC68HC08AZ32 motorola system integration module (sim) 89 sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. sim reset status register (srsr) this register contains six flags that show the source of the last reset. the sim reset status register can be cleared by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ?power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if stop or wait mode was exited by break. tst lobyte,sp ; if returnlo is not ?? bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to stop/wait opcode. return pulh rti ; restore h register. bit 7 654321 bit 0 srsr $fe01 read: por pin cop ilop ilad 0 lvi 0 write: por: 10000000 = unimplemented figure 17. sim reset status register (srsr) 21-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) MC68HC08AZ32 90 system integration module (sim) motorola pin ?external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ?computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ?illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ?illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ?low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr sim break flag control register (sbfcr) the sim break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ?break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break bit 7 654321 bit 0 sbfcr $fe03 read: bcfe rrrrrrr write: reset: 0 r = reserved for factory test figure 18. sim break flag control register (sbfcr) 22-sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola clock generator module (cgm) 91 clock generator module (cgm) cgm contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 phase-locked loop (pll) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . 97 manual and automatic pll bandwidth modes . . . . . . . . . . . . . . 97 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . 100 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . 102 external filter capacitor pin (cgmxfc). . . . . . . . . . . . . . . . . . . . . 102 pll analog power pin (vdda) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . 103 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . 103 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . 103 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 pll bandwidth control register (pbwc). . . . . . . . . . . . . . . . . . . . 107 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . . . . . 109 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 special modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 cgm during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 114 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 114 1-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 92 clock generator module (cgm) motorola parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . 115 choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (sim) derives the system clocks. cgmout is based on either the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with 1mhz to 8mhz crystals or ceramic resonators. the pll can generate an 8mhz bus frequency from an 8 mhz or a 4 mhz crystal. features features of the cgm include the following: phase-locked loop with output frequency in integer multiples of the crystal reference programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 2-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC08AZ32 motorola clock generator module (cgm) 93 functional description the cgm consists of three major submodules: crystal oscillator circuit which generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) which generates the programmable vco frequency clock cgmvclk. base clock selector circuit; this software-controlled circuit selects either cgmxclk divided by two or the vco clock cgmvclk divided by two, as the base clock cgmout. the sim derives the system clocks from cgmout. figure 1 shows the structure of the cgm. 3-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 94 clock generator module (cgm) motorola figure 1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog ? 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim, sci, mscan to sim ptc3 monitor mode a b s* user mode *when s = 1, cgmout = b 4-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC08AZ32 motorola clock generator module (cgm) 95 crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the output. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. an externally generated clock can also feed the osc1 pin of the crystal oscillator circuit. for this configuration, the external clock should be connected to the osc1 pin and the osc2 pin allowed to float. phase-locked loop (pll) circuit the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. register name bit 7 6 5 4321 bit 0 pll control register (pctl) pllie pllf pllon bcs 1111 pll bandwidth control register (pbwc) auto lock a cq xld 0000 pll programming register (ppg) mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 = unimplemented figure 2. cgm i/o register summary 5-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 96 clock generator module (cgm) motorola pll circuits the pll consists of the following circuits: voltage-controlled oscillator (vco) modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (4.9152mhz) times a linear factor l, or (l)f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a frequency f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency f rdv = f rclk . the vco? output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor n. the divider s output is the vco feedback clock, cgmvdv, running at a frequency f vdv = f vclk /n. (see programming the pll on page 99 for more information). the phase detector then compares the vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to cgmxfc based on the width and direction of the correction pulse. the filter can make fast or slow corrections depending on its mode, described in acquisition and tracking modes on page 97. the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the 6-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC08AZ32 motorola clock generator module (cgm) 97 speed of the lock detector is directly proportional to the final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ?in acquisition mode, the filter can make large frequency corrections to the vco. this mode is used at pll start-up or when the pll has suffered a severe noise hit and the resulting vco frequency is much different from the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. see pll bandwidth control register (pbwc) on page 107 tracking mode ?in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see base clock selector circuit on page 100 the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode is used also to determine when the vco clock, cgmvclk, is safe to use as the source for the base clock, cgmout. see pll bandwidth control register (pbwc) on page 107 if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll start-up, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. see base clock selector circuit . if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and 7-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 98 clock generator module (cgm) motorola the software must take appropriate action, depending on the application. (see interrupts on page 111 for information and precautions on using interrupts). the following conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see pll bandwidth control register (pbwc) on page 107) is a read-only indicator of the mode of the filter, see acquisition and tracking modes on page 97. the acq bit is set when the vco frequency is within a certain tolerance d trk and is cleared when the vco frequency is out with a certain tolerance d unt . (see acquisition/lock time specifications on page 114). the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance d lock and is cleared when the vco frequency is outgrowth a certain tolerance d unl . (see acquisition/lock time specifications on page 114). cpu interrupts can occur if enabled (pllie = 1) when the pll? lock condition changes, toggling the lock bit. (see pll control register (pctl) on page 105). the pll also may operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast start-up. the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see acquisition/lock time specifications on page 114), after turning on the pll by setting pllon in the pll control register (pctl). 8-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC08AZ32 motorola clock generator module (cgm) 99 software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. programming the pll the following procedure shows how to program the pll. note: the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency (four times the desired bus frequency). 3. choose a practical pll reference frequency, f rclk . 4. select a vco frequency multiplier, n. 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 6. select a vco linear range multiplier, l. where f nom = 4.9152mhz 7. calculate and verify the adequacy of the vco programmed center-of-range frequency f vrs . f vrs = (l)f nom f vclkdes 4f budes = n round f vclkdes f rclk -------------------------- - = f vclk nf rclk = f bus f vclk () 4 = l round f vclk f nom ---------------- - = 9-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 100 clock generator module (cgm) motorola 8. verify the choice of n and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application? tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note: exceeding the recommended maximum bus frequency or vco frequency can cause the mcu to ?rash? 9. program the pll registers accordingly: a. in the upper 4 bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower 4 bits of the pll programming register (ppg), program the binary equivalent of l. special programming exceptions the programming method described in programming the pll on page 99, does not account for two possible exceptions ?a value of zero for n or l is meaningless when used in the equations given. to account for these exceptions: a zero value for n is interpreted exactly the same as a value of one. a zero value for l disables the pll and prevents its selection as the source for the base clock. (see base clock selector circuit on page 100). base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the 10-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC08AZ32 motorola clock generator module (cgm) 101 selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a zero. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 3 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer? data for more information. figure 3 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f care should be taken with routing in order to minimize signal cross talk and noise. see acquisition/lock time specifications on page 114 for routing information and more information on the filter capacitor? value and its effects on pll performance. 11-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 102 clock generator module (cgm) motorola i/o signals the following paragraphs describe the cgm i/o signals. crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. figure 3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc1 v ssa cgmxfc v dda *r s can be zero (shorted) when used with higher-frequency crystals. refer to manufacturer? data. v dd 12-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) i/o signals MC68HC08AZ32 motorola clock generator module (cgm) 103 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. the pin should be connected to the same voltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator and pll. crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and is generated directly from the crystal oscillator circuit. figure 1 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at start-up. cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output (cgmxclk) divided by two or the vco clock (cgmvclk) divided by two. cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 13-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 104 clock generator module (cgm) motorola cgm registers the following registers control and monitor operation of the cgm: pll control register (pctl). (see pll control register (pctl) on page 105). pll bandwidth control register (pbwc). (see pll bandwidth control register (pbwc) on page 107). pll programming register (ppg). (see pll programming register (ppg) on page 109). figure 4 is a summary of the cgm registers . bit 7 654321 bit 0 pctl $001c read: pllie pllf pllon bcs 1111 write: pbwc $001d read: auto lock a cq xld 0000 write: ppg $001e read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: = unimplemented notes: 1. when auto = 0, pllie is forced to logic zero and is read-only. 2. when auto = 0, pllf and lock read as logic zero. 3. when auto = 1, a cq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic zero and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 4. cgm i/o register summary 14-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC08AZ32 motorola clock generator module (cgm) 105 pll control register (pctl) the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit . pllie ?pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as ?? reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ?pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit is set also. pllf always reads as ??when the auto bit in the pll bandwidth control register (pbwc) is clear. the pllf bit should be cleared by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: the pllf bit should not be inadvertently cleared. any read or read-modify-write operation on the pll control register clears the pllf bit. bit 7 654321 bit 0 pctl $001c read: pllie pllf pllon bcs 1111 write: reset: 00101111 = unimplemented figure 5. pll control register (pctl) 15-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 106 clock generator module (cgm) motorola pllon ?pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). see base clock selector circuit on page 100 reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ?base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to the other. during the transition, cgmout is held in stasis. see base clock selector circuit on page 100 reset and the stop instruction clear the bcs bit. 1 = cgmout driven by cgmvclk/2 0 = cgmout driven by cgmxclk/2 note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. see base clock selector circuit on page 100 pctl[3:0] ?unimplemented bits these bits provide no function and always read as ?? 16-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC08AZ32 motorola clock generator module (cgm) 107 pll bandwidth control register (pbwc) the pll bandwidth control register does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto ?automatic bandwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), the acq bit should be cleared before turning the pll on. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ?lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as ??and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked bit 7 654321 bit 0 pbwc $001d read: auto lock a cq xld 0000 write: reset: 00000000 = unimplemented figure 7. pll bandwidth control register (pbwc) 17-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 108 clock generator module (cgm) motorola acq ?acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ?crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit indicates whether the crystal reference frequency is active or not. to check the status of the crystal reference, the following procedure should be followed: 1. write a ??to xld. 2. wait 4 n cycles. (n is the vco frequency multiplier.) 3. read xld. 1 = crystal reference is not active 0 = crystal reference is active the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as ?? pbwc[3:0] ?reserved for test these bits enable test functions not available in user mode. to ensure software portability from development systems to user applications, software should write zeros to pbwc[3:0] whenever writing to pbwc. 18-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC08AZ32 motorola clock generator module (cgm) 109 pll programming register (ppg) the pll programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] ?multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. (see pll circuits on page 96 and programming the pll on page 99). a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). bit 7 654321 bit 0 ppg $001e read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 figure 8. pll programming register (ppg) table 7. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 19-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 110 clock generator module (cgm) motorola vrs[7:4] ?vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency f vrs . (see pll circuits on page 96, programming the pll on page 99, and pll control register (pctl) on page 105). 1 = vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see special programming exceptions on page 100). a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. (see base clock selector circuit on page 100 and special programming exceptions on page 100 for more information). reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failure of the pll to achieve lock. 20-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) interrupts MC68HC08AZ32 motorola clock generator module (cgm) 111 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as ?? software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency-sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select cgmvclk/2 as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 21-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 112 clock generator module (cgm) motorola special modes the wait and stop instructions put the mcu in low-power-consumption standby modes. wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. stop mode when the stop instruction executes, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock, cgmvclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the crystal clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. 22-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm during break interrupts MC68HC08AZ32 motorola clock generator module (cgm) 113 cgm during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see system integration module (sim) on page 69. to allow software to clear status bits during a break interrupt, a ??should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a ??to the bcfe bit. with bcfe at ??(its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 23-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 114 clock generator module (cgm) motorola acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time of the system, within specified tolerances, to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0hz to 1mhz, the acquisition time is the time taken for the frequency to reach 1mhz 50khz. 50khz = 5% of the 1mhz step input. if the system is operating at 1mhz and suffers a ?00khz noise hit, the acquisition time is the time taken to return from 900khz to 1mhz 5khz. 5khz = 5% of the 100khz step input. other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are as follows: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance d trk . acquisition time is based on an initial frequency error, (f des ? 24-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications MC68HC08AZ32 motorola clock generator module (cgm) 115 f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see manual and automatic pll bandwidth modes on page 97), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance d lock . lock time is based on an initial frequency error, (f des ?f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). see manual and automatic pll bandwidth modes on page 97. obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor 25-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) MC68HC08AZ32 116 clock generator module (cgm) motorola is too large, the pll may not be able to adjust the voltage in a reasonable time. see choosing a filter capacitor on page 116. also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. choosing a filter capacitor as described in parametric influences on reaction time on page 115, the external filter capacitor c f is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to the following equation: for the value of v dda , the voltage potential at which the mcu is operating should be used. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly available capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the c f c fact v dda f rdv --------------- - ? ? ?? = 26-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications MC68HC08AZ32 motorola clock generator module (cgm) 117 pll may become unstable. also, always choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. reaction time calculation the actual acquisition and lock times can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f , (see choosing a filter capacitor on page 116) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. see acquisition and tracking modes on page 97. note the inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode the acquisition and lock times are quantized into units based on the reference frequency. clock generator module (cgm) MC68HC08AZ32 118 clock generator module (cgm) motorola and the acquisition to lock time t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see base clock selector circuit on page 100), because the factors described in parametric influences on reaction time on page 115 may slow the lock time considerably. table 8. cgm component speci?ations characteristic symbol min typ. max notes crystal load capacitance c l consult crystal mfg. data crystal ?ed capacitance c f 2 * c l consult crystal mfg. data crystal tuning capacitance c 2 2 * c l consult crystal mfg. data feedback bias resistor r b 22m w series resistor r s 0 330k w 1m w not required filter capacitor c f ? fact * (v dda / f xclk ) filter capacitor multiply factor c fact 0.0154 f/sv f/sv bypass capacitor c byp 0.1 m f c byp must provide low ac impedance from f = f xclk /100 to 100 *f xclk , so series resistance must be considered 28-cgm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola mask options 119 mask options mask options contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 introduction this section describes the mask options and the two mask option registers. the mask options are hardwired connections specified at the same time as the rom code, which allow the user to customize the mcu. the options control the enable or disable of the following functions: resets caused by the lvi module power to the lvi module stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) rom security 1 stop instruction computer operating properly (cop) module enable eeprom security 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the rom data difficult for unauthorized users 1-maskops f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mask options MC68HC08AZ32 120 mask options motorola functional description lvistop ?lvi stop mode enable bit lvistop enables the lvi module in stop mode. see low-voltage inhibit (lvi) on page 149. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode sec ?rom security bit sec enables the rom security feature. setting the sec bit prevents access to the rom contents. 1 = rom security enabled 0 = rom security disabled lvirstd ?lvi reset disable bit lvirstd disables the reset signal from the lvi module. see low-voltage inhibit (lvi) on page 149. 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ?lvi power disable bit lvipwrd disables the lvi module. see low-voltage inhibit (lvi) on page 149 . 1 = lvi module power disabled 0 = lvi module power enabled bit 7 6 5 4 3 2 1 bit 0 mora $001f read: lvistop romsec lvirstd lvipwrd ssrec coprs stop copd write: r r rr rrrr reset: unaffected by reset figure 9. mask option register a (mora) 2-maskops f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mask options functional description MC68HC08AZ32 motorola mask options 121 ssrec ?short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096 cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles if using an external crystal oscillator, the ssrec bit should not be set. coprs ?cop rate select coprs is similar to copl (please note that the logic is reversed) as it determines the timeout period for the cop. 1 = cop timeout period is 2 18 ?2 4 cgmxclk cycles. 0 = cop timeout period is 2 13 ?2 4 cgmxclk cycles. stop ?stop enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ?cop disable bit copd disables the cop module. see computer operating properly module (cop) on page 143. 1 = cop module disabled 0 = cop module enabled 3-maskops f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mask options MC68HC08AZ32 122 mask options motorola eesec ?eeprom security enable bit. eesec enables the eeprom security function. setting eesec prevents program/erase access to locations $8f0 ?$8ff of the eeprom array and to the eeacr/eenvr configuration registers. see MC68HC08AZ32 eeprom security on page 45 1 = eeprom security function enabled 0 = eeprom security function disabled extra care should be exercised when selecting mask option registers since other hc08 family parts may have different options. if in doubt, check with your local field applications representative. bit 7 654321 bit 0 morb $003f read: eesec write: reset: unaffected by reset = unimplemented figure 10. mask option register b (morb) 4-maskops f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola break module 123 break module break module contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . 125 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 tim and pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 126 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 break status and control register (brkscr) . . . . . . . . . . . . . . . . 127 break address registers (brkh and brkl) . . . . . . . . . . . . . . . . . 128 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 introduction this section describes the break module. the break module can generate a break interrupt which stops normal program flow at a defined address in order to begin execution of a background program. 1-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module MC68HC08AZ32 124 break module motorola features features of the break module include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a ??to the brka bit in the break status and control register (brkscr). when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return from interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 11 shows the structure of the break module. 2-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module functional description MC68HC08AZ32 motorola break module 125 figure 11. break module block diagram flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see sim break flag control register (sbfcr) on page 90, and the break interrupts subsection for each module. iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) table 1. break i/o register summary register name bit 7 654321 bit 0 addr. break address register high (brkh) bit 15 14 13 12 11 10 9 bit 8 $fe0c break address register low (brkl) bit 7 654321 bit 0 $fe0d break status/control register (brkscr) brke brka $fe0e = unimplemented 3-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module MC68HC08AZ32 126 break module motorola cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. tim and pit during break interrupts a break interrupt stops the timer counter. cop during break interrupts the cop is disabled during a break interrupt when v hi is present on the rst pin. 4-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module break module registers MC68HC08AZ32 motorola break module 127 break module registers three registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status and control register (brkscr) the break status and control register contains break module enable and status bits. brke ?break enable bit this read/write bit enables breaks on break address register matches. brke is cleared by writing a ??to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ?break active bit this read/write status and control bit is set when a break address match occurs. writing a ??to brka generates a break interrupt. brka is cleared by writing a ??to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match bit 7 654321 bit 0 brkscr $fe0e read: brke brka 000000 write: reset: 00000000 = unimplemented figure 12. break status and control register (brkscr) 5-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module MC68HC08AZ32 128 break module motorola break address registers (brkh and brkl) the break address registers contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. bit 7 654321 bit 0 brkh $fe0c read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 brkl $fe0d read: bit 7 654321 bit 0 write: reset: 00000000 figure 13. break address registers (brkh and brkl) 6-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module low-power modes MC68HC08AZ32 motorola break module 129 low-power modes the wait and stop instructions put the mcu in low-power-consumption standby modes. wait mode if enabled, the break module is active in wait mode. the sim break stop/wait bit (sbsw) in the sim break status register indicates whether wait was exited by a break interrupt. if so, the user can modify the return address on the stack by subtracting one from it. (see system integration module (sim) on page 69). stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. a break interrupt will cause an exit from stop mode and sets the sbsw bit in the sim break status register. 7-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module MC68HC08AZ32 130 break module motorola 8-brk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola monitor rom (mon) 131 monitor rom (mon) monitor rom contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 introduction this section describes the monitor rom (mon08). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. 1-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 132 monitor rom (mon) motorola features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer up to 28.8k baud communication with host computer execution of code in ram or rom eeprom programming rom security functional description the monitor rom receives and executes commands from a host computer. figure 1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the MC68HC08AZ32 has a rom security feature to prevent external viewing of the contents of rom. proper procedures must be followed to verify rom content. access to the rom is denied to unauthorized users of customer specified software with security enabled. see security on page 141. user mode should be used to verify rom contents. in monitor mode, the mcu can execute host-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. 2-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC08AZ32 motorola monitor rom (mon) 133 figure 1. monitor mode circuit + + + 10 m w x1 v dd v dd a v hi mc145407 mc68hc125 68hc08 rst irq v dd a cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k w 0.1 m f 0.1 m f 10 w 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 m f 10 m f 10 m f 10 m f 1 2 4 7 14 3 0.1 m f 4.9152 mhz 10 k w ptc3 v dd 10 k w b a note: position a ?bus clock = cgmxclk ? 4 or cgmvclk ? 4 position b ?bus clock = cgmxclk ? 2 (see note.) 5 6 + v ssa ptc0 ptc1 10 k w 3-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 134 monitor rom (mon) motorola entering monitor mode table 1 shows the pin conditions for entering monitor mode. enter monitor mode by either executing a software interrupt instruction (swi) or applying a ??and then a ??to the rst pin. once out of reset, the mcu waits for the host to send eight security bytes (see security on page 141). after the security bytes, the mcu sends a break signal (10 consecutive ??) to the host computer, indicating that it is ready to receive a command. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v hi ( see 5.0 volt dc electrical characteristics on page 380), is applied to either the irq pin or the rst pin. see system integration module (sim) on page 69 for more information on modes of operation. note: holding the ptc3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 1. mode selection irq pin ptc0 pin ptc1 pin pta0 pin ptc3 pin mode cgmout bus frequency v hi 1011 monitor or v hi 1010 monitor cgmxclk cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- 4-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC08AZ32 motorola monitor rom (mon) 135 table 2 is a summary of the differences between user mode and monitor mode. data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 2 and figure 3 ). figure 2. monitor data format figure 3. sample monitor waveforms the data transmit and receive rate can be anywhere from 4800 baud to 28.8k baud. transmit and receive baud rates must be identical. table 2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd 1. if the high voltage (v hi ) is removed from the irq /v pp pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the mask option register. see 5.0 volt dc electrical characteristics on page 380. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 5-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 136 monitor rom (mon) motorola echoing the monitor rom immediately echoes each received byte back to the pta0 pin for error checking, as shown in figure 4 . figure 4. read transaction any result of a command appears after the echo of the last byte of the command. break signal a break signal is a start bit followed by nine low bits. this is shown in figure 4 . when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. commands the monitor rom uses the following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) addr. high read read addr. high addr. low addr. low data echo sent to monitor result figure 5. break transaction 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo 6-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC08AZ32 motorola monitor rom (mon) 137 table 3. read (read memory) command description read byte from memory operand speci?s 2-byte address in high byte:low byte order data returned returns contents of speci?d address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 4. write (write memory) command description write byte to memory operand speci?s 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data 7-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 138 monitor rom (mon) motorola table 5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand speci?s 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 6. iwrite (indexed write) command description write to last address accessed + 1 operand speci?s single data byte data returned none opcode $19 command sequence data iread iread data echo sent to monitor result data iwrite iwrite data echo sent to monitor 8-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC08AZ32 motorola monitor rom (mon) 139 a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64k byte memory map. baud rate with a 4.9152mhz crystal and the ptc3 pin at ??during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at ??during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by table 7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence table 8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence sp high readsp readsp sp low echo sent to monitor result run run echo sent to monitor 9-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 140 monitor rom (mon) motorola the mul[7:4] bits in the pll programming register (ppg). refer to clock generator module (cgm) on page 91. later revisions feature a monitor mode which is optimised to operate with either a 4.1952mhz crystal clock source (or multiples of 4.1952mhz) or a 4mhz crystal (or multiples of 4mhz). this supports designs which use the mscan module, which is generally clocked from a 4mhz, 8mhz or 16mhz crystal. the table below outlines the available baud rates for a range of crystals and how they can match to a pc baud rate. care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure. table 9. monitor baud rate selection monitor baud rate vco frequency multiplier (n) 123456 4.9152 mhz 4800 9600 14,400 19,200 24,000 28,800 4.194 mhz 4096 8192 12,288 16,384 20,480 24,576 table 10 baud rate closest pc baud pc error % clock freq ptc3=0 ptc3=1 ptc3=0 ptc3=1 ptc3=0 ptc3=1 32khz 57.97 28.98 57.6 28.8 0.64 0.63 1mhz 1811.59 905.80 1800 900 0.64 0.64 2mhz 3623.19 1811.59 3600 1800 0.64 0.64 4mhz 7246.37 3623.19 7200 3600 0.64 0.64 4.194mhz 7597.83 3798.91 7680 3840 1.08 1.08 4.9152mhz 8904.35 4452.17 8861 4430 0.49 0.50 8mhz 14492.72 7246.37 14400 7200 0.64 0.64 16mhz 28985.51 14492.75 28800 14400 0.64 0.64 10-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC08AZ32 motorola monitor rom (mon) 141 11-mon security a security feature discourages unauthorized reading of rom locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the byte locations $fff6?fffd. locations $fff6?fffd contain user-defined data. note: do not leave locations $fff6?fffd blank. for security reasons, enter data at locations $fff6?fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pa0. if the received bytes match those at locations $fff6?fffd, the host bypasses the security feature and can read all rom locations and execute code from rom. security remains bypassed until a power-on reset occurs. after the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. if the reset was not a power-on reset, security remains bypassed regardless of the data that the host sends. if the received bytes do not match the data at locations $fff6?fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading rom locations returns undefined data, and trying to execute code from rom causes an illegal address reset. after the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. after receiving the eight security bytes from the host, the mcu transmits a break character signalling that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) MC68HC08AZ32 142 monitor rom (mon) motorola figure 6. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 pa7 rst v dd 4096 + 32 cgmxclk cycles 24 cgmxclk cycles 256 cgmxclk cycles (one bit time) 1 4 1 1 2 1 break note: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 4 = wait 1 bit time before sending next byte. 4 from host from mcu 12-mon f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola computer operating properly module (cop) 143 computer operating properly module (cop) cop contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 stop instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 copctl write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 cop control register (copctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 cop module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 148 introduction this section describes the computer operating properly (cop) module, a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. cop resets can be prevented by periodically clearing the cop counter. 1-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly module (cop) MC68HC08AZ32 144 computer operating properly module (cop) motorola functional description figure 1 shows the structure of the cop module. figure 1. cop block diagram copctl write cgmxclk reset vector fetch reset status register internal reset sources (1) stop instruction clear bits 12? 12-bit cop prescaler clear all bits 6-bit cop counter copd (from mor) reset copctl write clear cop module copen (from sim) cop counter note:1. see active resets from internal sources on page 75. reset 2-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly module (cop) functional description MC68HC08AZ32 motorola computer operating properly module (cop) 145 the cop counter is a free-running 6-bit counter preceded by a12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 13 ?2 4 , or 2 18 ?2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs in mora. when coprs = 1, a 4.9152 mhz crystal, gives a cop timeout period of 53.3ms. writing any value to location $ffff before overflow occurs prevents a cop reset by clearing the cop counter and stages 5 through 12 of the prescaler. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr). see sim reset status register (srsr) on page 89.the cop should be cleared immediately before entering or after exiting stop mode to assure a full cop timeout period. a cpu interrupt routine can be used to clear the cop. note: cop clearing instructions should be placed in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. table 1. cop i/o register summary register name bit 7 654321 bit 0 addr. cop control register (copctl) $ffff 3-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly module (cop) MC68HC08AZ32 146 computer operating properly module (cop) motorola i/o signals the following paragraphs describe the signals shown in figure 1 . cgmxclk cgmxclk is the crystal oscillator output signal. the cgmxclk frequency is equal to the crystal frequency. stop instruction the stop instruction clears the cop prescaler. copctl write writing any value to the cop control register (copctl) (see cop control register (copctl) on page 147), clears the cop counter and clears bits 12 ?4 of the sim counter. reading the cop control register returns the reset vector. power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 cgmxclk cycles after power-up. internal reset an internal reset clears the cop prescaler and the cop counter. reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the mask option register (mora). see mask options on page 119 4-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly module (cop) cop control register (copctl) MC68HC08AZ32 motorola computer operating properly module (cop) 147 cop control register (copctl) the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. interrupts the cop does not generate cpu interrupt requests. monitor mode the cop is disabled in monitor mode when v hi is present on the irq pin or on the rst pin. bit 7 654321 bit 0 copctl $ffff read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 2. cop control register (copctl) 5-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly module (cop) MC68HC08AZ32 148 computer operating properly module (cop) motorola low-power modes the wait and stop instructions put the mcu in low-power-consumption standby modes. wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, the cop counter should be cleared periodically in a cpu interrupt routine. stop mode stop mode turns off the cgmxclk input to the cop and clears the cop prescaler. the cop should be serviced immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the mask option register (mor) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, the stop instruction should be disabled by programming the stop bit to ?? cop module during break interrupts the cop is disabled during a break interrupt when v hi is present on the rst pin. 6-cop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola low-voltage inhibit (lvi) 149 low-voltage inhibit (lvi) lvi contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 lvi interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 introduction this section describes the low-voltage inhibit module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 1-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) MC68HC08AZ32 150 low-voltage inhibit (lvi) motorola features features of the lvi module include the following: programmable lvi reset programmable power consumption digital filtering of vdd pin level note: if a low voltage interrupt (lvi) occurs during programming of eeprom memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. it is the responsibility of the user to ensure that in the event of an lvi any addresses being programmed receive specification programming conditions. functional description figure 1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwrd, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for 9 or more consecutive cpu cycles. note that short v dd spikes may not trip the lvi. it is the user? responsibility to ensure a clean v dd signal within the specified operating voltage range if normal microcontroller operation is to be guaranteed. lvipwrd and lvirstd are mask options. see mask options on page 119 . once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr . v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). 2-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) functional description MC68HC08AZ32 motorola low-voltage inhibit (lvi) 151 an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 1. lvi module block diagram polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bit. in the mask option register, the lvipwrd and lvirstd bits must be at ??to enable the lvi module and to enable the lvi resets. also, the lviprwd bit must be at ??to enable the lvi module, and the lvirstd bit must be at ??to disable lvi resets. forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the lvi tripf level and remains at or below that level for 9 or more consecutive cpu cycles. in the mask option register, the lvipwrd and lvirstd bits must be at ??to enable the lvi module and to enable lvi resets. table 1. lvi i/o register summary register name bit 7 654321 bit 0 addr. lvi status register (lvisr) lviout $fe0f = unimplemented low v dd lvirstd v dd > lvi trip = 0 v dd < lvi trip = 1 lviout lvipwrd detector v dd lvi reset (from mor) (from mor) v dd digital filter cpu clock anlgtrip 3-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) MC68HC08AZ32 152 low-voltage inhibit (lvi) motorola false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lvi module to reset the mcu,v dd must remain at or below the lvi tripf level for 9 or more consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. lvi status register (lvisr) the lvi status register flags v dd voltages below the lvi tripf level . lviout ?lvi output bit this read-only flag becomes set when v dd falls below the lvi tripf voltage for 32-40 cgmxclk cycles. (see table 2 ). reset clears the lviout bit. bit 7 654321 bit 0 lvisr $fe0f read: lviout 0000000 write: reset: 00000000 = unimplemented figure 2. lvi status register (lvisr) table 2. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > lvi tripr any 0 v dd < lv i tripf < 32 cgmxclk cycles 0 v dd < lv i tripf between 32 & 40 cgmxclk cycles 0 or 1 v dd < lv i tripf > 40 cgmxclk cycles 1 lv i tripf < v dd < lv i tripr any previous value 4-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) lvi interrupts MC68HC08AZ32 motorola low-voltage inhibit (lvi) 153 lvi interrupts the lvi module does not generate interrupt requests. low-power modes the wait instruction puts the mcu in low-power-consumption standby mode. wait mode when the lvipwrd mask option is programmed to ?? the lvi module is active after a wait instruction. when the lvirstd mask option is programmed to ?? the lvi module can generate a reset and bring the mcu out of wait mode. stop mode with lvistop=1 and lvipwrd=0 in the mora register, the lvi module will be active after a stop instruction. because cpu clocks are disabled during stop mode, the lvi trip must bypass the digital filter to generate a reset and bring the mcu out of stop. with the lvipwrd bit in the mora register at a logic 0 and the lvistop bit at a logic 0, the lvi module will be inactive after a stop instruction. note that the lvi feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application v dd voltage collapsing completely to an unsafe level. is is not intended that users operate the microcontroller at lower than the specified operating voltage, v dd . 5-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) MC68HC08AZ32 154 low-voltage inhibit (lvi) motorola 6-lvi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola external interrupt module (irq) 155 external interrupt module (irq) irq contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 160 irq status and control register (iscr) . . . . . . . . . . . . . . . . . . . . . . . 160 introduction the irq module provides the nonmaskable interrupt input. features features of the irq module include the following: dedicated external interrupt pins (irq ) irq interrupt control bit hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge 1-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) MC68HC08AZ32 156 external interrupt module (irq) motorola functional description a ??applied to any of the external interrupt pins can latch a cpu interrupt request. figure 3 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following occurs: vector fetch ?a vector fetch automatically generates an interrupt acknowledge signal which clears the latch that caused the vector fetch. software clear ?software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a ??to the ack1 bit clears the irq latch. reset ?a reset automatically clears the interrupt latch. figure 3. irq module block diagram all of the external interrupt pins are falling-edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. the mode1 bit in the iscr controls the triggering sensitivity of the irq pin. ack1 imask1 dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode1 voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus 2-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) functional description MC68HC08AZ32 motorola external interrupt module (irq) 157 when an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to ? the vector fetch or software clear may occur before or after the interrupt pin returns to ?? as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the modex1control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask1 bit in the iscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the corresponding imask bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. see figure 4 table 1. irq i/o register summary register name bit 7 6 5 4 3 2 1 bit 0 addr. irq status/control register (iscr) irqf ack1 imask1 mode1 $001a 3-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) MC68HC08AZ32 158 external interrupt module (irq) motorola . figure 4. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction. swi instruction? rti instruction? no stack cpu registers. no set i bit. load pc with interrupt vector. no yes unstack cpu registers. execute instruction. yes yes 4-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) functional description MC68HC08AZ32 motorola external interrupt module (irq) 159 irq pin a ??on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode1 bit is set, the irq pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the following actions must occur to clear the irq latch: vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a ??to the ack1 bit in the interrupt status and control register (iscr). the ack1 bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack1 bit can also prevent spurious interrupts due to noise. setting ack1 does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to ???as long as the irq pin is at ?? the irq latch remains set. the vector fetch or software clear and the return of the irq pin to ??may occur in any order. the interrupt request remains pending as long as the irq pin is at ?? a reset will clear the latch and the modex control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask1 bit, which makes it useful in applications where polling is preferred. the bih or bil instruction is used to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, false interrupts can be avoided by masking interrupt requests in the interrupt routine. 5-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) MC68HC08AZ32 160 external interrupt module (irq) motorola irq module during break interrupts the system integration module (sim) controls whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. see sim break flag control register (sbfcr) on page 90. to allow software to clear the irq latch during a break interrupt, a ??is written to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, a ??is written to the bcfe bit. with bcfe at ??(its default state), writing to the ack1 bit in the irq status and control register during the break state has no effect on the irq latch. irq status and control register (iscr) the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr performs the following functions: indicates the state of the irq interrupt flag clears the irq interrupt latch masks irq interrupt requests controls triggering sensitivity of the irq interrupt pin bit 7 6 5 4 3 2 1 bit 0 iscr $001a read: irqf 0 imask1 mode1 write: ack1 reset: 0000 0 000 = unimplemented figure 5. irq status and control register (iscr) 6-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) irq status and control register (iscr) MC68HC08AZ32 motorola external interrupt module (irq) 161 irqf ?irq flag this read-only status bit is high when the irq interrupt is pending. 1 = interrupt pending 0 = interrupt not pending ack1 ?irq interrupt request acknowledge bit writing a ??to this write-only bit clears the irq latch. ack1 always reads as ?? reset clears ack1. imask1 ?irq interrupt mask bit writing a ??to this read/write bit disables irq interrupt requests. reset clears imask1. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode1 ?irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq /v pp pin. reset clears mode1. 1 = interrupt requests on falling edges and low levels 0 = interrupt requests on falling edges only 7-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt module (irq) MC68HC08AZ32 162 external interrupt module (irq) motorola 8-irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola serial communications interface module (sci) 163 serial communications interface module (sci) sci contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 180 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 pte0/txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 sci control register 1 (scc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 sci control register 2 (scc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 sci control register 3 (scc3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 sci status register 1 (scs1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 sci status register 2 (scs2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 introduction this section describes the serial communications interface module, which allows high-speed asynchronous communications with peripheral devices and other mcus. 1-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 164 serial communications interface module (sci) motorola features features of the sci module include the following: full duplex operation standard mark/space non-return-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity two receiver wake-up methods: idle line wake-up address mark wake-up interrupt-driven operation with eight interrupt flags: transmitter empty transmission complete receiver full idle receiver input receiver overrun noise error framing error parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection 2-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 165 functional description figure 1 shows the structure of the sci module. the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 6 . table 1. sci i/o register summary register name bit 7 6 5 4 3 2 1 bit 0 addr. sci control register 1 (scc1) loops ensci txinv m wake ilty pen pty $0013 sci control register 2 (scc2) sctie tcie scrie ilie te re rwu sbk $0014 sci control register 3 (scc3) r8 t8 r r orie neie feie peie $0015 sci status register 1 (scs1) scte tc scrf idle or nf fe pe $0016 sci status register 2 (scs2) bkf rpf $0017 sci data register (scdr) $0018 sci baud rate register (scbr) scp1 scp0 scr2 scr1 scr0 $0019 = unimplemented r = reserved 3-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 166 serial communications interface module (sci) motorola figure 6. sci data formats bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit 4-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 167 figure 1. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wake-up pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci pte1/rxd pte2/txd internal bus txinv loops ? ?6 pre- scaler baud rate generator cgmxclk 5-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 168 serial communications interface module (sci) motorola transmitter figure 2 shows the structure of the sci transmitter. figure 2. sci transmitter character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). r scte pen pty h876543210l 11-bit transmit stop start t8 r scte sctie tcie sbk tc cgmxclk parity generation msb sci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register r tc sctie tcie scte transmitter cpu interrupt request reserved service request m ensci loops te pte2/txd txinv internal bus ? 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider ? 16 sctie 6-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 169 character transmission during an sci transmission, the transmit shift register shifts a character out to the pte0/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a ??to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a ??to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of ??. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a ??start bit automatically goes into the least significant bit position of the transmit shift register. a ??stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, ?? if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 7-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 170 serial communications interface module (sci) motorola break characters writing a ??to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all ?? and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at ?? transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one ?? the automatic ??at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by 8 or 9 ??data bits and a ??where the stop bit should be. receiving a break character has the following effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits table 2. sci transmitter i/o register summary register name bit 7 6 5 4321 bit 0 addr. sci control register 1 (scc1)loops ensci txinv m wake ilty pen pty $0013 sci control register 2 (scc2) sctie tcie scrie ilie te re rwu sbk $0014 sci control register 3 (scc3) r8 t8 r r orie neie feie peie $0015 sci status register 1 (scs1) scte tc scrf idle or nf fe pe $0016 sci data register (scdr) $0018 sci baud rate register (scbr) scp1 scp0 scr2 scr1 scr0 $0019 = unimplemented r = reserved 8-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 171 idle characters an idle character contains all ?? and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the pte2/txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note: when queueing an idle character, return the te bit to ??before the stop bit of the current character shifts out to the pte0/txd pin. setting te after the stop bit appears on pte0/txd causes data previously written to the scdr to be lost. a good time to toggle the te bit is when the scte bit becomes set and just before writing the next byte to the scdr. inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at ?? see sci control register 1 (scc1) on page 181. transmitter interrupts the following conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ?the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ?the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 9-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 172 serial communications interface module (sci) motorola receiver figure 3 shows the structure of the sci receiver. figure 3. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery r scrf or orie nf neie fe feie pe peie r scrie scrf ilie idle wake-up logic parity checking msb error cpu interrupt request reserved service request cpu interrupt request sci data register r8 r orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rxd internal bus pre- scaler baud divider ? 4 ? 16 scp1 scp0 scr2 scr1 scr0 cgmxclk scrie r 10-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 173 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). character reception during an sci reception, the receive shift register shifts characters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. table 3. sci receiver i/o register summary register name bit 7 6 5 4321 bit 0 addr. sci control register 1 (scc1)loops ensci txinv m wake ilty pen pty $0013 sci control register 2 (scc2) sctie tcie scrie ilie te re rwu sbk $0014 sci control register 3 (scc3) r8 t8 r r orie neie feie peie $0015 sci status register 1 (scs1) scte tc scrf idle or nf fe pe $0016 sci status register 2 (scs2) bkf rpf $0017 sci data register (scdr) $0018 sci baud rate register (scbr) scp1 scp0 scr2 scr1 scr0 $0019 = unimplemented r = reserved 11-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 174 serial communications interface module (sci) motorola data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 4 ): after every start bit after the receiver detects a data bit change from ??to ??(after the majority of data bit samples at rt8, rt9, and rt10 returns a valid ??and the majority of the next rt8, rt9, and rt10 samples returns a valid ??. to locate the start bit, data recovery logic does an asynchronous search for a ??preceded by three ??. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 4. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd 12-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 175 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 4 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 5 summarizes the results of the data bit samples. table 4. start bit veri?ation rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 13-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 176 serial communications interface module (sci) motorola note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are ?? following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 6 summarizes the results of the stop bit samples. table 5. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 6. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 14-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC08AZ32 motorola serial communications interface module (sci) 177 framing errors if the data recovery logic does not detect a ??where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no stop bit also sets the fe bit. receiver wake-up so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wake-up bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiver out of the standby state: address mark ?an address mark is a ??in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ?when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting ?? as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the pte1/rxd pin has been idle may cause the receiver to wake up immediately. 15-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 178 serial communications interface module (sci) motorola receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ?the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ?the idle bit in scs1 indicates that 10 or 11 consecutive ?? shifted in from the pte1/rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ?the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ?the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ?the fe bit in scs1 is set when a ??occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ?the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. 16-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) low-power modes MC68HC08AZ32 motorola serial communications interface module (sci) 179 low-power modes the wait and stop instructions put the mcu in low-power-consumption standby modes. wait mode the sci module remains active after the execution of a wait instruction. in wait mode the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. 17-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 180 serial communications interface module (sci) motorola sci during break module interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see sim break flag control register (sbfcr) on page 90. to allow software to clear status bits during a break interrupt, write a ?? to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a ??to the bcfe bit. with bcfe at 0 0 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at ?? after the break, doing the second step clears the status bit. i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ?transmit data pte1/rxd ?receive data pte0/txd (transmit data) the pte0/txd pin is the serial data output from the sci transmitter. the sci shares the pte0/txd pin with port e. when the sci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 18-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 181 i/o registers the following i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) sci control register 1 (scc1) sci control register 1 does the following: enables loop mode operation enables the sci controls output polarity controls character length controls sci wake-up method controls idle character detection enables parity function controls parity type bit 7 654321 bit 0 scc1 $0013 read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 figure 5. sci control register 1 (scc1) 19-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 182 serial communications interface module (sci) motorola loops ?loop mode select bit this read/write bit enables loop mode operation. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ?enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ?transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, including idle, break, start, and stop bits. m ?mode (character length) bit this read/write bit determines whether sci characters are 8 or 9 bits long (see table 7 ). the ninth bit can serve as an extra stop bit, as a receiver wake-up signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters 20-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 183 wake ?wake-up condition bit this read/write bit determines which condition wakes up the sci: a ?? (address mark) in the most significant bit position of a received character or an idle condition on the pte1/rxd pin. reset clears the wake bit. 1 = address mark wake-up 0 = idle line wake-up ilty ?idle line type bit this read/write bit determines when the sci starts counting ?? as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of ?? preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ?parity enable bit this read/write bit enables the sci parity function (see table 7 ). when enabled, the parity function inserts a parity bit in the most significant bit position (see figure 6 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ?parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity (see table 7 ). reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 21-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 184 serial communications interface module (sci) motorola sci control register 2 (scc2) sci control register 2 does the following: enables the following cpu interrupt requests: enables the scte bit to generate transmitter cpu interrupt requests enables the tc bit to generate transmitter cpu interrupt requests enables the scrf bit to generate receiver cpu interrupt requests enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wake-up transmits sci break characters table 7. character format selection control bits character format m pen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits 22-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 185 sctie ?sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. setting the sctie bit in scc3 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ?transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ?sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt bit 7 654321 bit 0 scc2 $0014 read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 figure 6. sci control register 2 (scc2) 23-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 186 serial communications interface module (sci) motorola ilie ?idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ?transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 ?? from the transmit shift register to the pte2/txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the pte0/txd returns to the idle condition (??. clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ?receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. 24-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 187 rwu ?receiver wake-up bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ?send break bit setting and then clearing this read/write bit transmits a break character followed by a ?? the ??after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no ?? between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately after setting the scte bit. toggling sbk too early causes the sci to send a break character instead of a preamble. sci control register 3 (scc3) sci control register 3 does the following: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables the following interrupts: receiver overrun interrupts noise error interrupts framing error interrupts parity error interrupts 25-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 188 serial communications interface module (sci) motorola r8 ?received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ?transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. orie ?receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie ?receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled. 0 = sci error cpu interrupt requests from ne bit disabled bit 7 6 5 4 3 2 1 bit 0 scc3 $0015 read: r8 t8 r r orie neie feie peie write: reset: u u 0 0 0000 = unimplemented u = unaffected r = reserved figure 7. sci control register 3 (scc3) 26-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 189 feie ?receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ?receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see sci status register 1 (scs1) on page 189). reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled sci status register 1 (scs1) sci status register 1 contains flags to signal the following conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error bit 7 654321 bit 0 scs1 $0016 read: scte tc scrf idle or nf fe pe write: reset: 11000000 = unimplemented figure 8. sci status register 1 (scs1) 27-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 190 serial communications interface module (sci) motorola scte ?sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ?transmission complete bit this read-only bit is set when the scte bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ?sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ?receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive ?? appear on the receiver input. idle generates an sci receive cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the 28-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 191 idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or ?receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 9 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ?receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected 29-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 192 serial communications interface module (sci) motorola fe ?receiver framing error bit this clearable, read-only bit is set when a logic is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ?receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected figure 9. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr (byte 2) scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr (byte 3) scrf = 0 byte 1 read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr (byte 3) delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 30-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 193 sci status register 2 (scs2) sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ?break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after ?? again appear on the pte1/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ?reception in progress flag bit this read-only bit is set when the receiver detects a ??during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress bit 7 654321 bit 0 scs2 $0017 read: bkf rpf write: reset: 00000000 = unimplemented figure 10. sci status register 2 (scs2) 31-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 194 serial communications interface module (sci) motorola sci data register (scdr) the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?0/t0 ?receive/transmit data bits reading address $0018 accesses the read-only received data bits, r7?0. writing to address $0018 writes the data to be transmitted, t7?0. reset has no effect on the sci data register. sci baud rate register (scbr) the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ?sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 8 . reset clears scp1 and scp0. bit 7 654321 bit 0 scdr $0018 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 11. sci data register (scdr) bit 7 654321 bit 0 scbr $0019 read: scp1 scp0 scr2 scr1 scr0 write: reset: 00000000 = unimplemented figure 12. sci baud rate register (scbr) 32-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC08AZ32 motorola serial communications interface module (sci) 195 scr2?cr0 ?sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 9 . reset clears scr2?cr0. use the following formula to calculate the sci baud rate: where: f xclk = clock frequency pd = prescaler divisor bd = baud rate divisor table 10 shows the sci baud rates that can be generated with a 4.9152-mhz crystal. table 8. sci baud rate prescaling scp1:0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 9. sci baud rate selection scr2:1:0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f xclk 64 pd bd ---------------------------------- - = 33-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) MC68HC08AZ32 196 serial communications interface module (sci) motorola table 10. sci baud rate selection examples scp1:0 prescaler divisor (pd) scr2:1:0 baud rate divisor (bd) baud rate (f xclk = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 34-sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola serial peripheral interface module (spi) 197 serial peripheral interface module (spi) spi contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 pin name conventions and i/o register addresses . . . . . . . . . . . . . . 199 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . 205 transmission format when cpha = ? . . . . . . . . . . . . . . . . . . . . . 205 transmission format when cpha = ? . . . . . . . . . . . . . . . . . . . . . 207 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 vss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 spi status and control register (spscr) . . . . . . . . . . . . . . . . . . . 226 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 1-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 198 serial peripheral interface module (spi) motorola introduction this section describes the serial peripheral interface module (spi, version c), which allows full-duplex, synchronous, serial communications with peripheral devices. features features of the spi module include the following: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency ? 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts with cpu service: sprf (spi receiver full) spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode ? 2 c (inter-integrated circuit) compatibility 2-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) pin name conventions and i/o register addresses MC68HC08AZ32 motorola serial peripheral interface module (spi) 199 pin name conventions and i/o register addresses the text that follows describes both spi1 and spi2. the spi i/o pin names are ss (slave select), spsck (spi serial clock), v ss (clock ground), mosi (master out slave in), and miso (master in slave out). the two spis share eight i/o pins with two parallel i/o ports. the full names of the spi i/o pins are as follows: the generic pins names appear in the text that follows. table 1. pin name conventions spi generic pin names: miso mosi ss sck v ss full spi pin names: spi pte5/miso pte6/mosi pte4/ss pte7/spsck cgnd table 2. i/o register addresses register name register address spi control register (spicr) $0010 spi status and control register (spiscr) $0011 spi data register (spidr) $0012 3-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 200 serial peripheral interface module (spi) motorola functional description figure 1 summarizes the spi i/o registers and figure 2 show the structure of the spi module. register name r/w bit 7 6 5 4 3 2 1 bit 0 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r = reserved figure 1. spi i/o register summary 4-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description MC68HC08AZ32 motorola serial peripheral interface module (spi) 201 figure 2. spi module block diagram the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. the following paragraphs describe the operation of the spi module. transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout ? 2 clock select ? 2 clock divider ? 8 ? 32 ? 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus (from sim) modfen errie control modf spmstr mosi miso spsck ss 5-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 202 serial peripheral interface module (spi) motorola master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: the spi modules should be configured as master and slave before they are enabled. also, the master spi should be enabled before the slave spi. similarly, disable the slave spi should be disabled before disabling the master spi. see spi control register (spcr) on page 223. only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 3 . the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. see spi status and control register (spscr) on page 226. through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master? miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with 6-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description MC68HC08AZ32 motorola serial peripheral interface module (spi) 203 sprf set and then reading the spi data register. writing to the spi data register clears the sptie bit. slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be at ?? ss must remain low until the transmission is complete. see mode fault error on page 212. in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software must then read the spi data register before another byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock that can be generated). the frequency of the spsck for an spi configured as a slave does not have to correspond to any particular spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. figure 3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss 7-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 204 serial peripheral interface module (spi) motorola a slave spi must complete the write to the data register at least one bus cycle before the master spi starts a transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see transmission formats on page 205. if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. note: spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 8-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC08AZ32 motorola serial peripheral interface module (spi) 205 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifting and sampling on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate a multiple-master bus contention. clock phase and polarity controls software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (cpha) control bit selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note: before writing to the cpol bit or the cpha bit, the spi should be disabled by clearing the spi enable bit (spe). transmission format when cpha = ?0? figure 4 shows an spi transmission in which cpha is ?? the figure should not be used as a replacement for data sheet parametric information.two waveforms are shown for sck: one for cpol = ??and another for cpol = ?? the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at ?? so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be 9-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 206 serial peripheral interface module (spi) motorola high or must be reconfigured as general purpose i/o not affecting the spi. see mode fault error on page 212. when cpha = ?? the first spsck edge is the msb capture strobe. therefore the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted. figure 4. transmission format (cpha = ?? figure 5. cpha/ss timing bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # (for reference) sck (cpol =?? sck (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha =?? slave ss (cpha = 1) 10-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC08AZ32 motorola serial peripheral interface module (spi) 207 transmission format when cpha = ?1? figure 6 shows an spi transmission in which cpha is ?? the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = ??and another for cpol = ?? the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at ?? so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. see mode fault error on page 212. when cpha = ?? the master begins driving its mosi pin on the first spsck edge. therefore the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 6. transmission format (cpha = ?? bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # (for reference) sck (cpol =?? sck (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe 11-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 208 serial peripheral interface module (spi) motorola transmission initiation latency when the spi is configured as a master (spmstr = ??, transmissions are started by a software write to the spdr. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = ?? the sck signal remains inactive for the first half of the first sck cycle. when cpha = ?? the first sck cycle begins with an edge on the sck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. see figure 7 . the internal spi clock in the master is a free-running derivative of the internal mcu clock. it is only enabled when both the spe and spmstr bits are set to conserve power. sck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr will occur relative to the slower sck. this uncertainty causes the variation in the initiation delay shown in figure 7 . this delay will be no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. 12-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC08AZ32 motorola serial peripheral interface module (spi) 209 figure 7. transmission start delay (master) write to spdr initiation delay bus mosi sck (cpha = 1 ) sck (cpha =?? sck cycle number msb bit 6 12 clock write to spdr earliest latest (sck = internal clock ? 2; earliest latest 2 possible start points) (sck = internal clock ? 8; 8 possible start points) earliest latest (sck = internal clock ? 32; 32 possible start points) earliest latest (sck = internal clock ? 128; 128 possible start points) write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? initiation delay from write spdr to transfer begin 13-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 210 serial peripheral interface module (spi) motorola error conditions the following flags signal spi error conditions: overflow (ovrf) ?failing to read the spi data register before the next byte enters the shift register results in the ovrf bit becoming set. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. mode fault error (modf) ?the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. overflow error the overflow flag (ovrf) becomes set if the spi receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. see figure 4 and figure 6 . if an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. therefore, an overflow error always indicates the loss of data. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. see figure 10 . it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without overflow interrupts enabled causes the mcu to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 8 shows how it is possible to miss an overflow. 14-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions MC68HC08AZ32 motorola serial peripheral interface module (spi) 211 figure 8. missed read of overflow condition the first part of figure 8 shows how to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf flag can be set in the interval between spscr and spdr being read. in this case, an overflow can easily be missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. to prevent this, the ovrf interrupt should be enabled, or alternatively another read of the spscr should be carried out following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will terminate with an sprf interrupt. figure 9 illustrates this process. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscrw with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is set. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. 15-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 212 serial peripheral interface module (spi) motorola figure 9. clearing sprf when ovrf interrupt is not enabled mode fault error for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. see figure 10 . it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss becomes ?? a mode fault in a master spi causes the following events to occur: read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. clearing ovrf bit. 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. 10 11 12 13 14 16-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions MC68HC08AZ32 motorola serial peripheral interface module (spi) 213 if errie = ?? the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port. note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = ?? reading spmstr when modf = ?? shows the difference between a modf occurring when the spi is a master and when it is a slave. when configured as a slave (spmstr = ??, the modf flag is set if ss goes high during a transmission. when cpha = ?? a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = ?? the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shift of the last data bit. see transmission formats on page 205. note: when cpha = ?? a modf occurs if a slave is selected (ss is at ?? and later deselected (ss is ?? even if no spsck is sent to that slave. this happens because ss at ??indicates the start of the transmission (miso driven out with the value of msb) for cpha = ?? when cpha = ?? a slave can be selected and then later deselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = ??, the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. 17-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 214 serial peripheral interface module (spi) motorola note: a ??on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, the spscr should be read with the modf bit set and then the spcr register should be written to. this entire clearing mechanism must occur with no modf condition existing or else the flag will not be cleared. interrupts four spi status flags can be enabled to generate cpu interrupt requests: the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt requests, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enables both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. table 3. spi interrupts flag request spte (transmitter empty) spi transmitter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (over?w) spi receiver/error interrupt request (sprie = 1, errie = 1) modf (mode fault) spi receiver/error interrupt request (sprie = 1, errie = 1, modfen = ?? 18-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) queuing transmission data MC68HC08AZ32 motorola serial peripheral interface module (spi) 215 figure 10. spi interrupt request generation two sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ?the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate either an spi receiver/error cpu interrupt request. spi transmitter empty (spte) ?the spte bit becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the spi data register only when the spte bit is high. figure 11 shows the timing spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request 19-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 216 serial peripheral interface module (spi) motorola associated with doing back-to-back transmissions with the spi (spsck has cpha: cpol = 1:0). for a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted. figure 11. sprf/spte cpu interrupt timing bit 3 mosi p sck (cpha:cpol =??0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. 20-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) resetting the spi MC68HC08AZ32 motorola serial peripheral interface module (spi) 217 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set any transmission currently in progress is aborted the shift register is cleared the spi state counter is cleared, making it ready for a new complete transmission all the spi port logic is defaulted back to being general purpose i/o. the following items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to set all control bits again when spe is set back high for the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing ??to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that was configured as a master with the modfen bit set. 21-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 218 serial peripheral interface module (spi) motorola low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, power consumption can be reduced by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs, the ovrf bit should be enabled to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see interrupts on page 214. stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 22-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) spi during break interrupts MC68HC08AZ32 motorola serial peripheral interface module (spi) 219 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see sim break flag control register (sbfcr) on page 90. to allow software to clear status bits during a break interrupt, a ??should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, a ??should be written to the bcfe bit. with bcfe at ??(its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is a ?? after the break, the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode will not initiate a transmission, nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 23-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 220 serial peripheral interface module (spi) motorola i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. miso ?data received mosi ?data transmitted spsck ?serial clock ?s ?slave select ? ss ?clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is ??and its ss pin is at ?? to support a multiple-slave system, a ??on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the miso pin regardless of the state of the data direction register of the shared i/o port. 24-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals MC68HC08AZ32 motorola serial peripheral interface module (spi) 221 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mosi pin regardless of the state of the data direction register of the shared i/o port. spsck (serial clock) the serial clock synchronizes data transmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = ?? the ss is used to define the start of a transmission. see transmission formats on page 205. since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = ??format. however, it can remain low throughout the transmission for the cpha = ??format. see figure 12 . figure 12. cpha/ss timing byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha =?? slave ss (cpha = ?? 25-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 222 serial peripheral interface module (spi) motorola when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. see spi status and control register (spscr) on page 226. note: a ??on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if transmission has already begun. when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. see mode fault error on page 212. for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. see table 4 . v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize radio frequency (rf) emissions, the ground pin should be connected of the slave to the v ss pin. table 4. spi con?uration spe spmstr modfen spi configuration state of ss logic 0x (1) x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi 1. x = don? care 26-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC08AZ32 motorola serial peripheral interface module (spi) 223 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) spi control register (spcr) the spi control register does the following: enables spi module interrupt requests selects cpu interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ?spi receiver interrupt enable this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled bit 7 6 5 4 3 2 1 bit 0 spcr read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 r = reserved figure 13. spi control register (spcr) 27-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 224 serial peripheral interface module (spi) motorola spmstr ?spi master this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ?clock polarity this read/write bit determines the logic state of the spsck pin between transmissions. see figure 4 and figure 6 . to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. cpha ?clock phase this read/write bit controls the timing relationship between the serial clock and spi data. see figure 4 and figure 6 . to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = ?? the ss pin of the slave spi module must be set to logic one between bytes. see figure 12 . reset sets the cpha bit. when cpha =??for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. when cpha = ??for a slave, the first edge of the spsck indicates the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. see mode fault error on page 212. a ??on the ss pin does not affect the state of the spi state machine in any way. spwom ?spi wired-or mode this read/write bit disables the pull-up devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 28-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC08AZ32 motorola serial peripheral interface module (spi) 225 0 = normal push-pull spsck, mosi, and miso pins spe ?spi enable this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. see resetting the spi on page 217. reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie?spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 29-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 226 serial peripheral interface module (spi) motorola spi status and control register (spscr) the spi status and control register contains flags to signal the following conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also contains bits that perform the following functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ?spi receiver full this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full bit 7 654321 bit 0 spscr read: sprf errie ovrf modf spte modfe n spr1 spr0 write: r rrr reset: 00001000 r = reserved figure 14. spi status and control register (spscr) 30-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC08AZ32 motorola serial peripheral interface module (spi) 227 errie ?error interrupt enable this read-only bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ?overflow flag this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow modf ?mode fault this clearable, ready-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi data register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ?spi transmitter empty this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note: the spi data register should not be written to unless the spte bit is high. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is 31-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 228 serial peripheral interface module (spi) motorola completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ?mode fault enable this read/write bit, when set to ?? allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general purpose i/o. if the modfen bit is set, then this pin is not available as a general purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general purpose i/o regardless of the value of modfen. see ss (slave select) on page 221. if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see mode fault error on page 212. spr1 and spr0 ?spi baud rate select in master mode, these read/write bits select one of four baud rates as shown in table 5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. table 5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 32-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC08AZ32 motorola serial peripheral interface module (spi) 229 the following formula is used to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor spi data register (spdr) the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. see figure 2 . r7:r0/t7:t0 ?receive/transmit data bits note: read-modify-write instructions should not be used on the spi data register since the buffer read is not the same as the buffer written. baud rate cgmout 2bd --------------------------- = bit 7 654321 bit 0 spdr read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 15. spi data register (spdr) 33-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) MC68HC08AZ32 230 serial peripheral interface module (spi) motorola 34-spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola timer interface module a (tima) 231 timer interface module a (tima) tima contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 pulse width modulation (pwm). . . . . . . . . . . . . . . . . . . . . . . . . . . 238 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . 239 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . 240 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 tima during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 tima clock pin (ptd6/taclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 tima channel i/o pins (ptf1/tach3?te2/tach0) . . . . . . . . . 245 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 tima status and control register (tasc) . . . . . . . . . . . . . . . . . . . 246 tima counter registers (tacnth:tacntl). . . . . . . . . . . . . . . . . 248 tima counter modulo registers (tamodh/l). . . . . . . . . . . . . . . . 249 tima channel status and control registers (tasc0?asc3) . . . . 250 tima channel registers (tach0h/l?achh/l). . . . . . . . . . . . . . 254 1-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 232 timer interface module a (tima) motorola introduction this section describes the timer interface module (tima). the tima is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 1 is a block diagram of the tima. features features of the tima include the following: four input capture/output compare channels rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tima clock input seven-frequency internal bus clock prescaler selection external tima clock input (4mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow tima counter stop and reset bits modular architecture expandable to 8 channels 2-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC08AZ32 motorola timer interface module a (tima) 233 functional description figure 1 shows the structure of the tima. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-counter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh:tamodl, control the modulo value of the tima counter. software can read the tima counter value at any time without affecting the counting sequence. the four tima channels are programmable independently as input capture or output compare channels. tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, ptd6/taclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tima status and control register select the tima clock source. 3-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 234 timer interface module a (tima) motorola figure 1. tima block diagram prescaler prescaler select taclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tach0h:tach0l ms0a els0b els0a pte2 tof toie inter- 16-bit comparator 16-bit latch tach1h:tach1l 16-bit comparator 16-bit latch tach2h:tach2l 16-bit comparator 16-bit latch tach3h:tach3l channel 0 channel 1 channel 2 channel 3 tamodh:tamodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bu s bus clock ms1a ms2a ms3a ptd6/taclk pte2/tach pte3/tach ptf0/tach ptf1/tach logic rupt logic inter- rupt logic pte3 logic inter- rupt logic ptf0 logic inter- rupt logic ptf1 logic inter- rupt logic 4-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC08AZ32 motorola timer interface module a (tima) 235 table 1. tima i/o register summary register name bit 7 6 5 4 3 2 1 bit 0 addr. tima status/control register (tasc) tof toie tstop trst 0 ps2 ps1 ps0 $0020 tima counter register high (tacnth) bit 15 14 13 12 11 10 9 bit 8 $0022 tima counter register low (tacntl) bit 7 6 5 4 3 2 1 bit 0 $0023 tima counter modulo reg. high (tamodh) bit 15 14 13 12 11 10 9 bit 8 $0024 tima counter modulo reg. low (tamodl) bit 7 6 5 4 3 2 1 bit 0 $0025 tima ch. 0 status/control register (tasc0) ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max$0026 tima ch. 0 register high (tach0h) bit 15 14 13 12 11 10 9 bit 8 $0027 tima ch. 0 register low (tach0l) bit 7 6 5 4 3 2 1 bit 0 $0028 tima ch. 1 status/control register (tasc1) ch1f ch1ie ms1a els1b els1a tov1 ch1max$0029 tima ch. 1 register high (tach1h) bit 15 14 13 12 11 10 9 bit 8 $002a tima ch. 1 register low (tach1l) bit 7 6 5 4 3 2 1 bit 0 $002b tima ch. 2 status/control register (tasc2) ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max$002c tima ch. 2 register high (tach2h) bit 15 14 13 12 11 10 9 bit 8 $002d tima ch. 2 register low (tach2l) bit 7 6 5 4 3 2 1 bit 0 $002e tima ch. 3 status/control register (tasc3) ch3f ch3ie ms3a els3b els3a tov3 ch3max$002f tima ch. 3 register high (tach3h) bit 15 14 13 12 11 10 9 bit 8 $0030 tima ch. 3 register low (tach3l) bit 7 6 5 4 3 2 1 bit 0 $0031 = unimplemented 5-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 236 timer interface module a (tima) motorola input capture with the input capture function, the tima can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tima latches the contents of the tima counter into the tima channel registers, tachxh:tachxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. output compare with the output compare function, the tima can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tima can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in output compare on page 236. the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tima may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. 6-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC08AZ32 motorola timer interface module a (tima) 237 when changing to a larger output compare value, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 registers initially controls the output on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (0 or 1) that control the output are the ones written to last. tasc0 controls and monitors the buffered output compare function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately control the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the output compare value in the tima channel 2 registers initially controls the output on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (2 or 3) that control the output are the ones written to last. tasc2 controls and monitors the buffered output compare function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. 7-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 238 timer interface module a (tima) motorola note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between overflows is the period of the pwm signal. as figure 2 shows, the output compare value in the tima channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the tima to set the pin if the state of the pwm pulse is logic zero. figure 2. pwm period and pulse width the value in the tima counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tima counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select pte/f/x/tachx period pulse width overflow overflow overflow output compare output compare output compare 8-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC08AZ32 motorola timer interface module a (tima) 239 value is $000. see tima status and control register (tasc) on page 246. the value in the tima channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50%. unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in pulse width modulation (pwm) on page 238. the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tima overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tima may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. 9-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 240 timer interface module a (tima) motorola note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pulse width are the ones written to last. tasc0 controls and monitors the buffered pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially control the pulse width on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (2 or 3) that control the pulse width are the ones written to last. tasc2 controls and monitors the buffered pwm function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. 10-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC08AZ32 motorola timer interface module a (tima) 241 note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by setting the tima stop bit, tstop. b. reset the tima counter by setting the tima reset bit, trst. 2. in the tima counter modulo registers (tamodh:tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh:tachxl), write the value for the required pulse width. 4. in tima channel x status and control register (tascx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 3 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 3 . note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 242 timer interface module a (tima) motorola 5. in the tima status control register (tasc), clear the tima stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tima channel 0 registers (tach0h:tach0l) initially control the buffered pwm output. tima status control register 0 (tascr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tima channel 2 registers (tach2h:tach2l) initially control the pwm output. tima status control register 2 (tascr2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. see tima channel status and control registers (tasc0?asc3) on page 250. 12-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) interrupts MC68HC08AZ32 motorola timer interface module a (tima) 243 interrupts the following tima sources can generate interrupt requests: tima overflow flag (tof) ?the tof bit is set when the tima counter value rolls over to $0000 after matching the value in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. tof and toie are in the tima status and control register. tima channel flags (ch3f?h0f) ?the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie= 1. chxf and chxie are in the tima channel x status and control register. low-power modes the wait instruction puts the mcu in low-power-consumption standby mode. wait mode the tima remains active after the execution of a wait instruction. in wait mode the tima registers are not accessible by the cpu. any enabled cpu interrupt request from the tima can bring the mcu out of wait mode. if tima functions are not required during wait mode, reduce power consumption by stopping the tima before executing the wait instruction. 13-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 244 timer interface module a (tima) motorola tima during break interrupts a break interrupt stops the tima counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see sim break flag control register (sbfcr) on page 90. to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 14-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o signals MC68HC08AZ32 motorola timer interface module a (tima) 245 i/o signals ports e and f each share two pins with the tim and port d shares one. ptd6/taclk is an external clock input to the tima prescaler. the four tima channel i/o pins are pte2/tach0, pte3/tach1, ptf0/tach2, and ptf1/tach3. tima clock pin (ptd6/taclk) ptd6/taclk is an external clock input that can be the clock source for the tima counter instead of the prescaled internal bus clock. select the ptd6/taclk input by writing logic ones to the three prescaler select bits, ps[2:0]. see tima status and control register (tasc) on page 246. the minimum taclk pulse width, taclk lmin or taclk hmin , is: the maximum tclk frequency is: ptd6/taclk is available as a general-purpose i/o pin when not used as the tima clock input. when the ptd6/taclk pin is the tima clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. tima channel i/o pins (ptf1/tach3epte2 /tach0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptf0/tach2 and pte3/tach1 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency --------------------------------- t su + bus frequency 2 ? 15-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 246 timer interface module a (tima) motorola i/o registers the following i/o registers control and monitor operation of the tima: tima status and control register (tasc) tima control registers (tacnth:tacntl) tima counter modulo registers (tamodh:tamodl) tima channel status and control registers (tasc0, tasc1, tasc2, and tasc3) tima channel registers (tach0h:tach0l, tach1h:tach1l, tach2h:tach2l, and tach3h:tach3l) tima status and control register (tasc) the tima status and control register does the following: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock bit 7 654321 bit 0 tasc $0020 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 3. tima status and control register (tasc) 16-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC08AZ32 motorola timer interface module a (tima) 247 tof ?tima overflow flag bit this read/write flag is set when the tima counter resets to $0000 after reaching the modulo value programmed in the tima counter modulo registers. clear tof by reading the tima status and control register when tof is set and then writing a logic zero to tof. if another tima overflow occurs before the clearing sequence is complete, then writing logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tima counter has reached modulo value 0 = tima counter has not reached modulo value toie ?tima overflow interrupt enable bit this read/write bit enables tima overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ?tima stop bit this read/write bit stops the tima counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before entering wait mode if the tima is required to exit wait mode. trst ?tima reset bit setting this write-only bit resets the tima counter and the tima prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tima counter is reset and always reads as logic zero. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. 17-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 248 timer interface module a (tima) motorola ps[2:0] ?prescaler select bits these read/write bits select either the ptd6/taclk pin or one of the seven prescaler outputs as the input to the tima counter as table 2 shows. reset clears the ps[2:0] bits. tima counter registers (tacnth:tacntl) the two read-only tima counter registers contain the high and low bytes of the value in the tima counter. reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears the tima counter registers note: if you read tacnth during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. table 2. prescaler selection ps[2:0] tima clock source 000 internal bus clock ? 1 001 internal bus clock ? 2 010 internal bus clock ? 4 011 internal bus clock ? 8 100 internal bus clock ? 16 101 internal bus clock ? 32 110 internal bus clock ? 64 111 ptd6/taclk 18-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC08AZ32 motorola timer interface module a (tima) 249 tima counter modulo registers (tamodh/l) the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the modulo value, the overflow flag (tof) becomes set, and the tima counter resumes counting from $0000 at the next clock. writing to the high byte (tamodh) inhibits the tof bit and overflow interrupts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before writing to the tima counter modulo registers. bit 7 654321 bit 0 tacnth $0022 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 tacntl $0023 read: bit 7 654321 bit 0 write: 00000000 reset: = unimplemented figure 4. tima counter registers (tacnth:tacntl) bit 7 654321 bit 0 tamodh $0024 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 bit 7 654321 bit 0 tamodl $0025 read: bit 7 654321 bit 0 write: reset: 11111111 figure 5. tima counter modulo registers (tamodh:tamodl) 19-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 250 timer interface module a (tima) motorola tima channel status and control registers (tasc0etasc3) each of the tima channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tima overflow selects 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation bit 7 654321 bit 0 tasc0 $0026 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0000000 0 bit 7 654321 bit 0 tasc1 $0029 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0000000 0 bit 7 654321 bit 0 tasc2 $002c read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0000000 0 bit 7 654321 bit 0 tasc3 $002f read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 0000000 0 = unimplemented figure 6. tima channel status and control registers (tasc0?asc3) 20-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC08AZ32 motorola timer interface module a (tima) 251 chxf?channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matches the value in the tima channel x registers. when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading tima channel x status and control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ?channel x interrupt enable bit this read/write bit enables tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ?mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tima channel 0 and tima channel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled 21-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 252 timer interface module a (tima) motorola msxa ?mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tbchx pin. see table 3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tima status and control register (tasc). elsxb and elsxa ?edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin ptex/tbchx is available as a general-purpose i/o pin. table 3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. 22-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC08AZ32 motorola timer interface module a (tima) 253 note: before enabling a tima channel register for input capture operation, make sure that the pte/tchxb pin is stable for at least two bus clocks. tovx ?toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggle on tima counter overflow. note: when tovx is set, a tima counter overflow takes precedence over a channel x output compare if both occur at the same time. table 3. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare 23-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 254 timer interface module a (tima) motorola chxmax ?channel x maximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 7 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 7. chxmax latency tima channel registers (tach0h/letachh /l) these read/write registers contain the captured tima counter value of the input capture function or the output compare value of the output compare function. the state of the tima channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the tima channel x registers (tachxh) inhibits output compares until the low byte (tachxl) is written. output overflow pte/f/x/tachx period chxmax overflow overflow overflow overflow compare output compare output compare output compare bit 7 654321 bit 0 tach0h $0027 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 8. tima channel registers (tach0h/l?ach3h/l) 24-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC08AZ32 motorola timer interface module a (tima) 255 bit 7 654321 bit 0 tach0l $0028 read: bit 7 654321 bit 0 write: reset: indeterminate after reset bit 7 654321 bit 0 tach1h $002a read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset bit 7 654321 bit 0 tach1l $002b read: bit 7 654321 bit 0 write: reset: indeterminate after reset bit 7 654321 bit 0 tach2h $002d read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset bit 7 654321 bit 0 tach2l $002e read: bit 7 654321 bit 0 write: reset: indeterminate after reset bit 7 654321 bit 0 tach3h $0030 reset: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset bit 7 654321 bit 0 tach3l $0031 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 8. tima channel registers (tach0h/l?ach3h/l) (continued) 25-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) MC68HC08AZ32 256 timer interface module a (tima) motorola 26-tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola timer interface module b (timb) 257 timer interface module b (timb) timb contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . 262 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . 264 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . 265 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 timb during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 timb clock pin (ptd4/tblck). . . . . . . . . . . . . . . . . . . . . . . . . . . 269 timb channel i/o pins (ptf5/tbch1?tf4/tbch0) . . . . . . . . . 269 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 timb status and control register (tbsc) . . . . . . . . . . . . . . . . . . . 270 timb counter registers (tbcnth:tbcntl). . . . . . . . . . . . . . . . . 272 timb counter modulo registers (tbmodh:tbmod) . . . . . . . . . . 273 timb channel status and control registers (tbsc0?bsc1) . . . . 274 timb channel registers (tbch0h/ l?bch3h/l) . . . . . . . . . . . . 278 1-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 258 timer interface module b (timb) motorola introduction this section describes the timer interface module (timb). the timb is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 9 is a block diagram of the timb. features features of the timb include the following: two input capture/output compare channels rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable timb clock input seven-frequency internal bus clock prescaler selection external timb clock input (4-mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow timb counter stop and reset bits modular architecture expandable to 8 channels 2-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC08AZ32 motorola timer interface module b (timb) 259 functional description figure 9 shows the structure of the timb. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-counter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh:tbmodl, control the modulo value of the timb counter. software can read the timb counter value at any time without affecting the counting sequence. the two timb channels are programmable independently as input capture or output compare channels. timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, ptd4/tbclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the timb status and control register select the timb clock source. 3-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 260 timer interface module b (timb) motorola figure 9. timb block diagram prescaler prescaler select tbclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tbch0h:tbch0l ms0a els0b els0a ptf2 tof toie inter- 16-bit comparator 16-bit latch tbch1h:tbch1l channel 0 channel 1 tbmodh:tbmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a ptd4/tbclk ptf4/tbch ptf5/tbch logic rupt logic inter- rupt logic ptf3 logic inter- rupt logic cantimcap cantimcap 4-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC08AZ32 motorola timer interface module b (timb) 261 input capture with the input capture function, the timb can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timb latches the contents of the timb counter into the timb channel registers, tbchxh:tbchxl. the polarity of the active edge is programmable. input captures can generate timb cpu interrupt requests. output compare with the output compare function, the timb can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the timb can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in output compare on page 261. the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timb overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timb may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. 5-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 262 timer interface module b (timb) motorola when changing to a larger output compare value, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately control the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 registers initially controls the output on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tbsc0 controls and monitors the buffered output compare function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between overflows is the period of the pwm signal. 6-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC08AZ32 motorola timer interface module b (timb) 263 as figure 10 shows, the output compare value in the timb channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the timb to set the pin if the state of the pwm pulse is logic zero. the value in the timb counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timb counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see timb status and control register (tbsc) on page 270. the value in the timb channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50%. figure 10. pwm period and pulse width ptfx/tbchx period pulse width overflow overflow overflow output compare output compare output compare 7-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 264 timer interface module b (timb) motorola unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in pulse width modulation (pwm) on page 262. the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a timb overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timb may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 8-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC08AZ32 motorola timer interface module b (timb) 265 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (0 or 1) that control the pulse width are the ones written to last. tbsc0 controls and monitors the buffered pwm function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by setting the timb stop bit, tstop. b. reset the timb counter by setting the timb reset bit, trst. 2. in the timb counter modulo registers (tbmodh:tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh:tbchxl), write the value for the required pulse width. 4. in timb channel x status and control register (tbscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 1 b. write 1 to the toggle-on-overflow bit, tovx. 9-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 266 timer interface module b (timb) motorola c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 1 ) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb status control register (tbsc), clear the timb stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the timb channel 0 registers (tbch0h:tbch0l) initially control the buffered pwm output. timb status control register 0 (tbscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. see timb channel status and control registers (tbsc0?bsc1) on page 274. 10-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) interrupts MC68HC08AZ32 motorola timer interface module b (timb) 267 interrupts the following timb sources can generate interrupt requests: timb overflow flag (tof) ?the tof bit is set when the timb counter value rolls over to $0000 after matching the value in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. tof and toie are in the timb status and control register. timb channel flags (ch1f?h0f) ?the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the timb channel x status and control register. low-power modes the wait instruction puts the mcu in low-power-consumption standby mode. wait mode the timb remains active after the execution of a wait instruction. in wait mode the timb registers are not accessible by the cpu. any enabled cpu interrupt request from the timb can bring the mcu out of wait mode. if timb functions are not required during wait mode, reduce power consumption by stopping the timb before executing the wait instruction. 11-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 268 timer interface module b (timb) motorola timb during break interrupts a break interrupt stops the timb counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see sim break flag control register (sbfcr) on page 90. to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 12-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o signals MC68HC08AZ32 motorola timer interface module b (timb) 269 i/o signals port f shares two of its pins with the timb and port d shares one. ptd4/tbclk is an external clock input to the timb prescaler. the two timb channel i/o pins are ptf4/tbch0 and ptf5/tbch1. timb clock pin (ptd4/tblck) ptd4/tbclk is an external clock input that can be the clock source for the timb counter instead of the prescaled internal bus clock. select the ptd4/tbclk input by writing logic ones to the three prescaler select bits, ps[2:0]. see timb status and control register (tbsc) on page 270. the minimum tbclk pulse width, tbclk lmin or tbclk hmin , is: the maximum tclk frequency is: is available as a general-purpose i/o pin when not used as the timb clock input. when the ptd4/tbclk pin is the timb clock input, it is an input regardless of the state of the ddr5 bit in data direction register d. timb channel i/o pins (ptf5/tbch1eptf4/ tbch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptf5/tbch1 and ptf4/tbch0 can be configured as buffered output compare or buffered pwm pins. tbch0 has an additional source for the input capture signal i.e cantimcap. see figure 9 this signal is generated by the mscan08 which generates a timer signal whenever a valid frame has been received or transmitted. the signal is routed into tbch0 under the control of the timer link enable (tlnken) bit in the cmcr0 see 23.12.2 mscan08 module control register (cmcr0). 1 bus frequency --------------------------------- t su + bus frequency 2 ? 13-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 270 timer interface module b (timb) motorola i/o registers the following i/o registers control and monitor operation of the tim: timb status and control register (tbsc) timb control registers (tbcnth:tbcntl) timb counter modulo registers (tbmodh:tbmodl) timb channel status and control registers (tbsc0 and tbsc1) timb channel registers (tbch0h:tbch0l and tbch1h:tbch1l) timb status and control register (tbsc) the timb status and control register does the following: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock 14-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC08AZ32 motorola timer interface module b (timb) 271 tof ?timb overflow flag bit this read/write flag is set when the timb counter resets to $0000 after reaching the modulo value programmed in the timb counter modulo registers. clear tof by reading the timb status and control register when tof is set and then writing a logic zero to tof. if another timb overflow occurs before the clearing sequence is complete, then writing logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = timb counter has reached modulo value 0 = timb counter has not reached modulo value toie ?timb overflow interrupt enable bit this read/write bit enables timb overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ?timb stop bit this read/write bit stops the timb counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before entering wait mode if the timb is required to exit wait mode. bit 7 654321 bit 0 tbsc $0040 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 11. timb status and control register (tbsc) 15-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 272 timer interface module b (timb) motorola trst ?timb reset bit setting this write-only bit resets the timb counter and the timb prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timb counter is reset and always reads as logic zero. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. ps[2:0] ?prescaler select bits these read/write bits select either the ptd5 pin or one of the seven prescaler outputs as the input to the timb counter as table 1 shows. reset clears the ps[2:0] bits. timb counter registers (tbcnth:tbcntl) the two read-only timb counter registers contain the high and low bytes of the value in the timb counter. reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears the timb counter registers. table 1. prescaler selection ps[2:0] timb clock source 000 internal bus clock ? 1 001 internal bus clock ? 2 010 internal bus clock ? 4 011 internal bus clock ? 8 100 internal bus clock ? 16 101 internal bus clock ? 32 110 internal bus clock ? 64 111 ptd4/tblck 16-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC08AZ32 motorola timer interface module b (timb) 273 note: if you read tbcnth during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. timb counter modulo registers (tbmodh:tbmod) the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the modulo value, the overflow flag (tof) becomes set, and the timb counter resumes counting from $0000 at the next clock. writing to the high byte (tbmodh) inhibits the tof bit and overflow interrupts until the low byte (tbmodl) is written. reset sets the timb counter modulo registers. bit 7 654321 bit 0 tbcnth $0041 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 tbcntl $0042 read: bit 7 654321 bit 0 write: 00000000 reset: = unimplemented figure 12. timb counter registers (tbcnth:tbcntl) bit 7 654321 bit 0 tbmodh $0043 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 bit 7 654321 bit 0 tbmodl $0044 read: bit 7 654321 bit 0 write: reset: 11111111 figure 13. timb counter modulo registers (tbmodh:tbmodl) 17-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 274 timer interface module b (timb) motorola note: reset the timb counter before writing to the timb counter modulo registers. timb channel status and control registers (tbsc0etbsc1) each of the timb channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on timb overflow selects 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation bit 7 654321 bit 0 tbsc0 $0045 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0000000 0 bit 7 654321 bit 0 tbsc1 $0048 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0000000 0 reset: 0000000 0 = unimplemented figure 14. timb channel status and control registers (tbsc0?bsc1) 18-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC08AZ32 motorola timer interface module b (timb) 275 chxf?channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matches the value in the timb channel x registers. when timb cpu interrupt requests are enabled (chxie=1), clear chxf by reading timb channel x status and control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ?channel x interrupt enable bit this read/write bit enables timb cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ?mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timb channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. 1 = reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ?mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 1 . 1 = unbuffered output compare/pwm operation 0 = input capture operation 19-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 276 timer interface module b (timb) motorola when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. see table 1 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the timb status and control register (tsc). elsxb and elsxa ?edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port f, and pin ptfx/tbchx is available as a general-purpose i/o pin. table 1 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 1. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare 20-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC08AZ32 motorola timer interface module b (timb) 277 note: before enabling a timb channel register for input capture operation, make sure that the ptfx/tbchx pin is stable for at least two bus clocks. tovx ?toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggle on timb counter overflow. note: when tovx is set, a timb counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ?channel x maximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 15 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stabs at the 100% duty cycle level until the cycle after chxmax is cleared. figure 15. chxmax latency output overflow ptfx/tbchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare 21-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) MC68HC08AZ32 278 timer interface module b (timb) motorola timb channel registers (tbch0h/ letbch3h/l) these read/write registers contain the captured timb counter value of the input capture function or the output compare value of the output compare function. the state of the timb channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the timb channel x registers (tbchxh) inhibits output compares until the low byte (tbchxl) is written. bit 7 654321 bit 0 tbch0h $0046 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset bit 7 654321 bit 0 tbch0l $0047 read: bit 7 654321 bit 0 write: reset: indeterminate after reset bit 7 654321 bit 0 tbch1h $0049 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset bit 7 654321 bit 0 tbch1l $004a read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 16. timb channel registers (tbch0h/l?bch1h/l) 22-timb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola programmable interrupt timer (pit) 279 programmable interrupt timer (pit) pit contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 pit status and control register (psc) . . . . . . . . . . . . . . . . . . . . . . 283 pit counter registers (pcnth:pcntl) . . . . . . . . . . . . . . . . . . . . 285 pit counter modulo registers (pmodh:pmodl) . . . . . . . . . . . . 286 introduction this section describes the periodic interrupt timer module (pit). figure 1 is a block diagram of the pit. features features of the pit include the following: programmable pit clock input free-running or modulo up-count operation pit counter stop and reset bits 1-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) MC68HC08AZ32 280 programmable interrupt timer (pit) motorola functional description figure 1 shows the structure of the pit. the central component of the pit is the 16-bit pit counter that can operate as a free-running counter or a modulo up-counter. the counter provides the timing reference for the interrupt. the pit counter modulo registers, pmodh:pmodl, con- trol the modulo value of the counter. software can read the counter value at any time without affecting the counting sequence. figure 1. pit block diagram prescaler prescaler select internal 16-bit comparator pps2 pps1 pps0 pof pie interrupt pittmodh:pittmodl crst cstop 16-bit counter bus clock logic table 1. pit i/o register summary register name bit 7 654321 bit 0 addr. pit status/control register (psc) pof pie pstop prst 0 pps2 pps1 pps0 $004b pit counter register. high (pcnth) bit 15 14 13 12 11 10 9 8 $004c pit counter register. low (pcntl) 76543210 $004d pit counter modulo reg. high (pmodh) bit 15 14 13 12 11 10 9 bit 8 $004e pit counter modulo reg. low (pmodl) bit 7 654321 bit 0 $004f 2-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) low-power modes MC68HC08AZ32 motorola programmable interrupt timer (pit) 281 pit counter prescaler the clock source can be one of the seven prescaler outputs. the pres- caler generates seven clock rates from the internal bus clock. the pres- caler select bits, pps[2:0] in the status and control register select the pit clock source. the value in the pit counter modulo registers and the selected pres- caler output determines the frequency of the periodic interrupt. the pit over?w ?g (pof) is set when the pit counter value rolls over to $0000 after matching the value in the pit counter modulo registers. the pit interrupt enable bit, pie, enables pit over?w cpu interrupt requests. pof and pie are in the pit status and control register. low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the pit remains active after the execution of a wait instruction. in wait mode the pit registers are not accessible by the cpu. any enabled cpu interrupt request from the pit can bring the mcu out of wait mode. if pit functions are not required during wait mode, reduce power con- sumption by stopping the pit before executing the wait instruction. stop mode the pit is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the pit counter. pit operation resumes when the mcu exits stop mode after an external interrupt. 3-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) MC68HC08AZ32 282 programmable interrupt timer (pit) motorola pit during break interrupts a break interrupt stops the pit counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break ?g control register (sbfcr) enables software to clear status bits during the break state. see sim break ?g control register (sbfcr) on page 90. to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the ?st step on such a bit before the break, the bit can- not change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 4-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) i/o registers MC68HC08AZ32 motorola programmable interrupt timer (pit) 283 i/o registers the following i/o registers control and monitor operation of the pit: pit status and control register (psc) pit counter registers (pcnth:pcntl) pit counter modulo registers (pmodh:pmodl) pit status and control register (psc) the pit status and control register does the following: enables pit interrupt flags pit over?ws stops the pit counter resets the pit counter prescales the pit counter clock bit 7 654321 bit 0 psc $004b read: pof pie pstop 00 pps2 pps1 pps0 write: 0 prst reset: 00100000 = unimplemented figure 2. pit status and control register (tsc) 5-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) MC68HC08AZ32 284 programmable interrupt timer (pit) motorola pof ?pit overflow flag bit this read/write flag is set when the pit counter resets to $0000 after reaching the modulo value programmed in the pit counter modulo registers. clear pof by reading the pit status and control register when pof is set and then writing a logic zero to pof. if another pit overflow occurs before the clearing sequence is complete, then writing logic zero to pof has no effect. therefore, a pof interrupt request cannot be lost due to inadvertent clearing of pof. reset clears the pof bit. writing a logic one to pof has no effect. 1 = pit counter has reached modulo value 0 = pit counter has not reached modulo value pie ?pit overflow interrupt enable bit this read/write bit enables pit overflow interrupts when the pof bit becomes set. reset clears the pie bit. 1 = pit overflow interrupts enabled 0 = pit overflow interrupts disabled pstop ?pit stop bit this read/write bit stops the pit counter. counting resumes when pstop is cleared. reset sets the pstop bit, stopping the pit counter until software clears the pstop bit. 1 = pit counter stopped 0 = pit counter active note: do not set the pstop bit before entering wait mode if the pit is required to exit wait mode. prst ?pit reset bit setting this write-only bit resets the pit counter and the pit prescaler. setting prst has no effect on any other registers. counting resumes from $0000. prst is cleared automatically after the pit counter is reset and always reads as logic zero. reset clears the prst bit. 1 = prescaler and pit counter cleared 0 = no effect note: setting the pstop and prst bits simultaneously stops the pit counter at a value of $0000. 6-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) i/o registers MC68HC08AZ32 motorola programmable interrupt timer (pit) 285 pps[2:0] ?prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the pit counter as table 2 shows. reset clears the pps[2:0] bits. pit counter registers (pcnth:pcntl) the two read-only pit counter registers contain the high and low bytes of the value in the pit counter. reading the high byte (pcnth) latches the contents of the low byte (pcntl) into a buffer. subsequent reads of pcnth do not affect the latched pcntl value until pcntl is read. reset clears the pit counter registers. setting the pit reset bit (prst) also clears the pit counter registers. note: if you read pcnth during a break interrupt, be sure to unlatch pcntl by reading pcntl before exiting the break interrupt. otherwise, pcntl retains the value latched during the break. table 2. prescaler selection ps[2:0] pit clock source 000 internal bus clock ? 1 001 internal bus clock ? 2 010 internal bus clock ? 4 011 internal bus clock ? 8 100 internal bus clock ? 16 101 internal bus clock ? 32 110 internal bus clock ? 64 111 internal bus clock ? 64 7-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) MC68HC08AZ32 286 programmable interrupt timer (pit) motorola pit counter modulo registers (pmodh:pmodl) the read/write pit modulo registers contain the modulo value for the pit counter. when the pit counter reaches the modulo value, the over- ?w ?g (pof) becomes set, and the pit counter resumes counting from $0000 at the next clock. writing to the high byte (pmodh) inhibits the pof bit and over?w interrupts until the low byte (pmodl) is writ- ten. reset sets the pit counter modulo registers. note: reset the pit counter before writing to the pit counter modulo registers. bit 15 14 13 12 11 10 9 bit 8 pcnth $004c read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 pcntl $004d read: bit 7 654321 bit 0 write: 00000000 reset: = unimplemented figure 3. pit counter registers (pcnth:pcntl) bit 15 14 13 12 11 10 9 bit 8 pmodh $004e read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 bit 7 654321 bit 0 pmodl $004f read: bit 7 654321 bit 0 write: reset: 11111111 figure 4. pit counter modulo registers (tmodh:tmodl) 8-pit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola analog-to-digital converter (adc) 287 analog-to-digital converter (adc) adc contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 adc analog power pin (vddaref) . . . . . . . . . . . . . . . . . . . . . . . 293 adc analog ground pin (avss/vrefl) . . . . . . . . . . . . . . . . . . . . 293 adc voltage reference pin (vrefh) . . . . . . . . . . . . . . . . . . . . . . 293 adc voltage in (advin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 adc status and control register (adscr) . . . . . . . . . . . . . . . . . . 294 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 adc clock register (adclkr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 1-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 288 analog-to-digital converter (adc) motorola introduction this section describes the analog to digital converter. the adc is an eight bit analog to digital converter. features features of the adc module include the following: 8 or 15 channels with multiplexed input linear successive approximation 8 bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 2-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description MC68HC08AZ32 motorola analog-to-digital converter (adc) 289 functional description eight or fifteen adc channels are available for sampling external sources at pins ptd6/taclk?td0 and ptb7/atd7?tb0/atd0. an analog multiplexer allows the single adc converter to select one adc channel as adc voltage in (adcvin). adcvin is converted by the successive approximation register based counter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 1 . figure 1. adc block diagram internal data b u s read ddrb write ddrb reset write ptb read ptb/ptd ptbx/ptdx ddrbx/ddrdx ptbx/ptdx interrupt logic channel select adc clock generator conversion complete adc voltage in (advin) adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable (adc channel x) 3-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 290 analog-to-digital converter (adc) motorola adc port i/o pins ptd6/taclk?td0 and ptb7/atd7?tb0/atd0 are general purpose i/o pins that share with the adc channels. the channel select bits define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic zero. note: do not use adc channels atd14 or atd12 when using the ptd6/taclk or ptd4/tblck pins as the clock inputs for the 16-bit timers. voltage conversion when the input voltage to the adc equals to vrefh, the adc converts the signal to $ff (full scale). if the input voltage equals to a vss /vrefl , the adc converts it to $00. input voltages between vrefh and a vss /vrefl is a straight-line linear conversion. conversion accuracy of all other input voltages is not guaranteed. current injection on unused pins can also cause conversion inaccuracies. note: input voltage should not exceed the analog supply voltages. conversion time conversion starts after a write to the adscr. conversion time in terms of the number of bus cycles is a function of oscillator frequency, bus frequency, and adiv prescaler bits. for example, with oscillator frequency of 4mhz, bus frequency of 8mhz and adc clock frequency of 1mhz, one conversion will take between 16 adc and 17 adc clock cycles or between 16 and 17 ? in this case. there will be 128 bus cycles between each conversion. sample rate is approximately 60khz. conversion time = # bus cycles = conversion time x bus frequency 16?7 adc cycles adc frequency 4-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) interrupts MC68HC08AZ32 motorola analog-to-digital converter (adc) 291 continuous conversion in the continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after the first conversion and will stay set for the next several conversions until the next write of the adc status and control register or the next read of the adc data register. accuracy and precision the conversion process is monotonic and has no missing codes. interrupts when the aien bit is set, the adc module is capable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bit is at logic zero. the coco bit is not used as a conversion complete flag when interrupts are enabled. 5-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 292 analog-to-digital converter (adc) motorola low power modes the wait and stop instruction can put the mcu in low power consumption standby modes. wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch[4:0] bits in the adc status and control register before executing the wait instruction. stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabilize the analog circuitry. 6-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o signals MC68HC08AZ32 motorola analog-to-digital converter (adc) 293 i/o signals the adc module has 8 or 15 i/o that are shared with port b and port d. adc analog power pin (v ddaref ) the adc analog portion uses as its power pin. connect the v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddaref for good results. note: route v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. v ddaref must be present for operation of he adc. adc analog ground pin (a vss /vrefl) the adc analog portion uses a vss /vrefl as its ground pin. connect the a vss /vrefl pin to the same voltage potential as v ss . adc voltage reference pin (vrefh) vrefh is the reference voltage for the adc. adc voltage in (advin) advin is the input voltage signal from one of the 8 or 15 adc channels to the adc module. 7-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 294 analog-to-digital converter (adc) motorola i/o registers the following i/o registers control and monitor operation of the adc: adc status and control register (adscr) adc data register (adr) adc clock register (adclk) adc status and control register (adscr) the following paragraphs describe the function of the adc status and control register. coco ?conversions complete when aien bit is a logic zero, the coco is a read only bit which is set each time a conversion is completed except in the continuous conversion mode where it is set after the first conversion. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. if aien bit is a logic one, the coco is a read bit which selects the cpu to service the adc interrupt request. reset clears this bit. 1 = conversion completed (aien=0) or cpu interrupt enabled (aien=1) 0 = conversion not completed (aien=0) or cpu interrupt enabled (aien=1) bit 7 654321 bit 0 adscr $0038 read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: r reset: 00011111 figure 2. adc status and control register 8-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers MC68HC08AZ32 motorola analog-to-digital converter (adc) 295 aien ?adc interrupt enable when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ?adc continuous conversion when set, the adc will continuously convert samples and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ?adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bit field which is used to select one of the adc channels. the channels are detailed in the following table. care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. see table 1 . the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when the adc is not used. note: recovery from the disabled state requires one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applications. 9-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 296 analog-to-digital converter (adc) motorola table 1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptd0 01001 ptd1 01010 ptd2 01011 ptd3 01100 ptd4/tblck 01101 ptd5 01110 ptd6/taclk range 01111 ($0f) to 11010 ($1a) unused (see note 1) unused (see note 1) 11011 reserved 1 1 1 0 0 unused (see note 1) 1 1 1 0 1 v refh (see note 2) 1 1 1 1 0 v ssa /v refl (see note 2) 1 1 1 1 1 [adc power off] notes: 1. if any unused channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as speci?d in the table are used to verify the operation of the adc converter both in production test and for user applications. 10-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers MC68HC08AZ32 motorola analog-to-digital converter (adc) 297 adc data register (adr) one 8-bit result register is provided. this register is updated each time an adc conversion completes. adc clock register (adclkr) this register selects the clock frequency for the adc adiv2:adiv0 ?adc clock prescaler bits adiv2, adiv1and adiv0 form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 2 shows the available clock configurations. the adc clock should be set to approximately 1mhz. bit 7 654321 bit 0 adr $0039 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: 00000000 = unimplemented figure 3. adc data register bit 7 654321 bit 0 adclk $003a read: adiv2 adiv1 adiv0 adiclk 0000 write: reset: 00000000 = unimplemented figure 4. adc clock register 1mhz cgmxclk or bus frequency adiv 2:0 [] -------------------------------------------------------------- = 11-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) MC68HC08AZ32 298 analog-to-digital converter (adc) motorola adiclk ?adc input clock select adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal or greater than 1mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less than 1mhz, use the pll generated bus clock as the clock source. as long as the internal adc clock is at approximately 1mhz, correct operation can be guaranteed. see conversion time on page 290. 1 = internal bus clock 0 = external clock (cgmxclk) note: during the conversion process, changing the adc clock will result in an incorrect conversion. table 2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock /1 0 0 1 adc input clock / 2 0 1 0 adc input clock / 4 0 1 1 adc input clock / 8 1 x x adc input clock / 16 x = don? care 12-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola keyboard module (kb) 299 keyboard module (kb) keyboard module contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 keyboard status and control register (kbscr) . . . . . . . . . . . . . . 303 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . . . . . 304 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . . 305 introduction the keyboard module provides five independently maskable external interrupt pins. features features of the keyboard module include the following: five keyboard interrupt pins and interrupt masks selectable triggering sensitivity 1-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) MC68HC08AZ32 300 keyboard module (kb) motorola functional description writing to the kbie4?bie0 bits in the keyboard interrupt enable register independently enables or disables each port g or port h pin as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its pull-up device. a logic zero applied to a keyboard interrupt pin can latch a keyboard interrupt request. the keyboard interrupt latch becomes set when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering sensitivity of the keyboard interrupt latch. if the keyboard interrupt latch is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, software can disable the former pin while it is low. if the keyboard interrupt latch is edge- and level-sensitive, an interrupt request is latched as long as any keyboard pin is low. figure 5. keyboard module block diagram kb4ie kb0ie ptg4/ kbd4 ptg0/ kbd0 to pullup enable to pullup enable keyboard interrupt dq ck clr v dd modek synchronizer imaskk keyboard interrupt request vector fetch decoder ackk internal bus latch 2-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) functional description MC68HC08AZ32 motorola keyboard module (kb) 301 the modek bit in the keyboard status and control register controls the triggering sensitivity of the keyboard interrupt latch. if the modek bit is set, the keyboard interrupt pins are both falling-edge- and low-level-sensitive, and both of the following actions must occur to clear the keyboard interrupt latch: vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic one to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt latch. writing to the ackk bit can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffd2 and $ffd3. return of all enabled keyboard interrupt pins to logic one ?as long as any enabled keyboard interrupt pin is at logic zero, the keyboard interrupt latch remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic one may occur in any order. the interrupt request remains pending as long as any enabled keyboard interrupt pin is at logic zero. table 1. kb i/o register summary register name bit 7 654321 bit 0 addr. keyboard status/control register (kbscr) r:0000 keyf 0 imask k mode k $001b w: ackk reset 00000000 keyboard interrupt control register (kbicr) r:000 kb4ie kb3ie kb2ie kb1ie kb0ie $0021 w: reset 00000000 = unimplemented 3-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) MC68HC08AZ32 302 keyboard module (kb) motorola if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt latch. reset clears the keyboard interrupt latch and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic zero. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bit (kbxie) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic zero for software to read the pin. 4-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) i/o registers MC68HC08AZ32 motorola keyboard module (kb) 303 i/o registers the following registers control and monitor operation of the keyboard module: keyboard status and control register (kbscr) keyboard interrupt enable register (kbier) keyboard status and control register (kbscr) the keyboard status and control register performs the following functions: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard latch triggering sensitivity bits 7? ?not used these read-only bits always read as logic zeros. keyf ?keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending bit 7 654321 bit 0 kbscr $001b read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 = unimplemented figure 6. keyboard status and control register (kbscr) 5-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) MC68HC08AZ32 304 keyboard module (kb) motorola ackk ?keyboard acknowledge bit writing a logic one to this read/write bit clears the keyboard interrupt latch. ackk always reads as logic zero. reset clears ackk. imaskk ?keyboard interrupt mask bit writing a logic one to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests disabled 0 = keyboard interrupt requests enabled modek ?keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only keyboard interrupt enable register (kbier) the keyboard interrupt enable register enables or disables each port g or port h pin to operate as a keyboard interrupt pin. kbie4:kbie0 ?keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = pin enabled as keyboard interrupt pin 0 = pin not enabled as keyboard interrupt pin bit 7 654321 bit 0 kbier $0021 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset 00000000 = unimplemented figure 7. keyboard interrupt enable register (kbier) 6-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) keyboard module during break interrupts MC68HC08AZ32 motorola keyboard module (kb) 305 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic one to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), writing during the break state to the keyboard acknowledge bit (ackk) in the keyboard status and control register has no effect. see keyboard status and control register (kbscr) on page 303. 7-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard module (kb) MC68HC08AZ32 306 keyboard module (kb) motorola 8-kbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola i/o ports 307 i/o ports i/o ports contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 port a data register (pta). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . 309 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 port b data register (ptb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . 312 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . . . . . 315 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . . . . . 318 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 port e data register (pte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . . . . . 322 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . . . . . . . 325 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 data direction register g (ddrg) . . . . . . . . . . . . . . . . . . . . . . . . . 327 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 data direction register h (ddrh) . . . . . . . . . . . . . . . . . . . . . . . . . 329 1-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 308 i/o ports motorola introduction forty-nine bidirectional input-output (i/o) pins form eight parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. table 1. i/o port register summary register name bit 7 654321 bit 0 addr. port a data register (pta) pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 $0000 port b data register (ptb) ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 $0001 port c data register (ptc) 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 $0002 port d data register (ptd) ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 $0003 data direction register a (ddra) ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 $0004 data direction register b (ddrb) ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 $0005 data direction register c (ddrc)mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 $0006 data direction register d (ddrd) ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 $0007 port e data register (pte) pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 $0008 port f data register (ptf) 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 $0009 port g data register (ptg) 0 0000 ptg2 ptg1 ptg0 $000a port h data register (pth) 0 00000 pth1 pth0 $000b data direction register e (ddre) ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 $000c data direction register f (ddrf) 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 $000d data direction register g (ddrg) 0 0000 ddrg2 ddrg1 ddrg0 $000e data direction register h (ddrh) 0 00000 ddrh1 ddrh0 $000f 2-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port a MC68HC08AZ32 motorola i/o ports 309 port a port a is an 8-bit general-purpose bidirectional i/o port. port a data register (pta) the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ?port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. data direction register a (ddra) data direction register a determines whether each port a pin is an input or an output. writing a logic one to a ddra bit enables the output buffer for the corresponding port a pin; a logic zero disables the output buffer. ddra[7:0] ?data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input bit 7 654321 bit 0 pta $0000 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 1. port a data register (pta) bit 7 654321 bit 0 ddra $0004 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 figure 2 data direction register a (ddra) 3-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 310 i/o ports motorola note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 3 shows the port a i/o logic. figure 3. port a i/o circuit when bit ddrax is a logic one, reading address $0000 reads the ptax data latch. when bit ddrax is a logic zero, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 2 summarizes the operation of the port a pins. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus table 2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) input, hi-z (2) ddra[7:0] pin pta[7:0] (3) 1 x output ddra[7:0] pta[7:0] pta[7:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 4-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port b MC68HC08AZ32 motorola i/o ports 311 port b port b is an 8-bit special function port that shares all of its pins with the analog to digital convertor. port b data register (ptb) the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ?port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. atd[7:0] ?adc channels note: ptb7/atd7?ptb0/atd0 are eight analog to digital convertor channels. the adc channel select bits, ch[4:0], determine whether the ptb7/atd7?tb0/atd0 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be zero if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. data direction register b (ddrb) does not affect the data direction of port b pins that are being used by the adc. however, the ddrb bits always determine whether reading port b returns the states of the latches or logic 0. bit 7 654321 bit 0 ptb $0001 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate functions atd7 atd6 atd5 atd4 atd3 atd2 atd1 atd0 figure 4. port b data register (ptb) 5-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 312 i/o ports motorola data direction register b (ddrb) data direction register b determines whether each port b pin is an input or an output. writing a logic one to a ddrb bit enables the output buffer for the corresponding port b pin; a logic zero disables the output buffer. ddrb[7:0] ?data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 6 shows the port b i/o logic. bit 7 654321 bit 0 ddrb $0005 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 figure 5. data direction register b (ddrb) figure 6. port b i/o circuit read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus 6-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port b MC68HC08AZ32 motorola i/o ports 313 when bit ddrbx is a logic one, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic zero, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 3 summarizes the operation of the port b pins. table 3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) input, hi-z (2) ddrb[7:0] pin ptb[7:0] (3) 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 7-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 314 i/o ports motorola port c port c is a 6-bit general-purpose bidirectional i/o port. port c data register (ptc) the port c data register contains a data latch for each of the six port c pins. ptc[5:0] ?port c data bits these read/write bits are software-programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. mclk ?t12 system clock the system clock is driven out of ptc2 when enabled by mclken. bit 7 654321 bit 0 ptc $0002 read: 00 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternate functions mclk = unimplemented figure 7. port c data register (ptc) 8-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port c MC68HC08AZ32 motorola i/o ports 315 data direction register c (ddrc) data direction register c determines whether each port c pin is an input or an output. writing a logic one to a ddrc bit enables the output buffer for the corresponding port c pin; a logic zero disables the output buffer. mclken ?mclk enable bit this read/write bit enables mclk to be an output signal on ptc2. if mclk is enabled, ptc2 is under the control of mclken. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled ddrc[5:0] ?data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. figure 9 shows the port c i/o logic. bit 7 654321 bit 0 ddrc $0006 read: mclke n 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 = unimplemented figure 8. data direction register c (ddrc) 9-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 316 i/o ports motorola when bit ddrcx is a logic one, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic zero, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 4 summarizes the operation of the port c pins. . figure 9. port c i/o circuit read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus table 4. port c pin functions bit value ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc[7] pin ptc2 1 2 output ddrc[7] 0 0x (1) input, hi-z (2) ddrc[5:0] pin ptc[5:0] (3) 1 x output ddrc[5:0] ptc[5:0] ptc[5:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 10-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port d MC68HC08AZ32 motorola i/o ports 317 port d port d is an 8-bit general-purpose i/o port. port d data register (ptd) port d is an 8 -bit special function port that shares seven of it? pins with the analog to digital converter and two with the tima and timb modules. ptd[7:0] ?port d data bits ptd[7:0] are read/write, software programmable bits. data direction of ptd[7:0] pins are under the control of the corresponding bit in data direction register d. data direction register d determines whether each port d pin is an input or an output. writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a logic zero disables the output buffer atd[14:8] ?adc channel status bits ptd6/atd14/taclk?td0/atd8 are seven of the 15 analog-to-digital converter channels. the atd channel select bits, ch[4:0], determine whether the ptd6/atd14/taclk?td0/atd8 pins are adc channels or general purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. otherwise the data will reflect the value in the data latch. note: data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the tima or timb. however, the bit 7 654321 bit 0 ptd $0003 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternate functions r atd14/ taclk atd13 atd12/ tbclk atd11 atd10 atd9 atd8 figure 10. port d data register (ptd) 11-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 318 i/o ports motorola ddrd bits always determine whether reading port d returns the states of the latches to logic 0. taclk/tbclk ?timer clock input the ptd6/taclk pin is the external clock input for the tima. the ptd4/tbclk pin is the external clock input for the timb.the prescaler select bits, ps[2:0], select ptd6/taclk or ptd4/tbclk as the tim clock input (see tima channel status and control registers (tasc0?asc3) on page 250 and timb status and control register (tbsc) on page 270). when not selected as the tim clock, ptd6/taclk and ptd4/tbclk are available for general purpose i/o. while taclk/tbclk are selected, corresponding ddrd bits have no effect. data direction register d (ddrd) data direction register d determines whether each port d pin is an input or an output. writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a logic zero disables the output buffer. ddrd[7:0] ?data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 12 shows the port d i/o logic. when bit ddrdx is a logic one, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic zero, reading address $0003 bit 7 654321 bit 0 ddrd $0007 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 figure 11. data direction register d (ddrd) 12-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port d MC68HC08AZ32 motorola i/o ports 319 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 5 summarizes the operation of the port d pins. figure 12. port d i/o circuit read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus table 5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) input, hi-z (2) ddrd[7:0] pin ptd[7:0] (3) 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 13-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 320 i/o ports motorola port e port e is an 8-bit special function port that shares two of its pins with the timer interface module (tima), two of its pins with the serial communications interface module (sci) and four of its pins with the serial peripheral interface module (spi). port e data register (pte) the port e data register contains a data latch for each of the eight port e pins. pte[7:0] ?port e data bits pte[7:0] are read/write, software programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. spsck ?spi serial clock the pte7/spsck pin is the serial clock input of a spi slave module and serial clock output of a spi master modules. when the spe bit is clear, the pte7/spsck pin is available for general-purpose i/o. mosi ?master out/slave in the pte6/mosi pin is the master out/slave in terminal of the spi module. when the spe bit is clear, the pte6/mosi pin is available for general-purpose i/o. see spi control register (spcr) on page 223. bit 7 654321 bit 0 pte $0008 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternate function: spsck mosi miso ss tach1 tach0 rxd txd figure 13. port e data register (pte) 14-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port e MC68HC08AZ32 motorola i/o ports 321 miso ?master in/slave out the pte5/miso pin is the master in/slave out terminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pte5/miso pin is available for general-purpose i/o. see spi control register (spcr) on page 223. ss ?slave select the pte4/ss pin is the slave select input of the spi module. when the spe bit is clear, or when the spi master bit, spmstr, is set, the pte4/ss pin is available for general-purpose i/o. see spi control register (spcr) on page 223. when the spi is enabled as a slave, the ddrf0 bit in data direction register e (ddre) has no effect on the pte4/ss pin. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 6 . tach[1:0] ?timer a channel i/o bits the pte3/tach1?te2/tach0 pins are the tima input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pte3/tach1?te2/tach0 pins are timer channel i/o pins or general-purpose i/o pins. see tima channel status and control registers (tasc0?asc3) on page 250. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tima. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 6 . rxd ?sci receive data input the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see sci control register 1 (scc1) on page 181. 15-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 322 i/o ports motorola txd ?sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see sci control register 2 (scc2) on page 184. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 6 . data direction register e (ddre) data direction register e determines whether each port e pin is an input or an output. writing a logic one to a ddre bit enables the output buffer for the corresponding port e pin; a logic zero disables the output buffer. ddre[7:0] ?data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 15 shows the port e i/o logic. when bit ddrex is a logic one, reading address $0008 reads the ptex data latch. when bit ddrex is a logic zero, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 6 summarizes the operation of the port e pins. bit 7 654321 bit 0 ddre $000c read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 figure 14. data direction register e (ddre) 16-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port e MC68HC08AZ32 motorola i/o ports 323 figure 15. port e i/o circuit read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus table 6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) input, hi-z (2) ddre[7:0] pin pte[7:0] (3) 1 x output ddre[7:0] pte[7:0] pte[7:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 17-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 324 i/o ports motorola port f port f is a 7-bit special function port that shares four of its pins with the timer interface module (tima-6) and two of its pins with the timer interface module (timb)). port f data register (ptf) the port f data register contains a data latch for each of the seven port f pins. ptf[6:0] ?port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on ptf[6:0]. tach[5:2] ?timer a channel i/o bits the ptf3/tach5?tf0/tach2 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf3/tach5?tf0/tach2 pins are timer channel i/o pins or general-purpose i/o pins. bit 7 654321 bit 0 ptf $0009 read: 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternate function: tbch1 tbch0 tach5 tach4 tach3 t a ch2 = unimplemented figure 16. port f data register (ptf) 18-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port f MC68HC08AZ32 motorola i/o ports 325 tbch[1:0] ?timer b channel i/o bits the ptf5/tbch1-ptf4/tbch0 pins are the timb input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf5/tbch1-ptf4/tbch0 pins are timer channel i/o pins or general purpose i/o pins. see timb status and control register (tbsc) on page 270. note: data direction register f(ddrf) does not affect the data direction of port f pins that are being used by tima and timb. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. see table 7 . data direction register f (ddrf) data direction register f determines whether each port f pin is an input or an output. writing a logic one to a ddrf bit enables the output buffer for the corresponding port f pin; a logic zero disables the output buffer. ddrf[6:0] ?data direction register f bits these read/write bits control port f data direction. reset clears ddrf[6:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. bit 7 654321 bit 0 ddrf $000d read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 0000000 = unimplemented figure 17. data direction register f (ddrf) 19-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 326 i/o ports motorola figure 18 shows the port f i/o logic. when bit ddrfx is a logic one, reading address $0009 reads the ptfx data latch. when bit ddrfx is a logic zero, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 7 summarizes the operation of the port f pins. figure 18. port f i/o circuit read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus table 7. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0x (1) input, hi-z (2) ddrf[6:0] pin ptf[6:0] (3) 1 x output ddrf[6:0] ptf[6:0] ptf[6:0] 1. x = don? care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. 20-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port g MC68HC08AZ32 motorola i/o ports 327 port g port g is a 3-bit general-purpose bidirectional i/o port. port g data register (ptg) the port g data register contains a data latch for each of the three port g pins. ptg[2:0] ?port g data bits these read/write bits are software-programmable. data direction of each bit is under the control of the corresponding bit in data direction register g. reset has no effect on port g data. kbd[2:0] ?keyboard inputs the keyboard interrupt enable bits, kbie[2:0], in the keyboard interrupt control register (kbicr), enable the port g pins as external interrupt pins. see keyboard module (kb) on page 299. data direction register g (ddrg) data direction register g determines whether each port g pin is an input or an output. writing a logic one to a ddrg bit enables the output buffer for the corresponding port g pin; a logic zero disables the output buffer. bit 7 654321 bit 0 ptg $000a read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset alternate function kbd2 kbd1 kbd0 = unimplemented figure 19. port g data register (ptg) bit 7 654321 bit 0 ddrg $000e read: 00000 ddrg2 ddrg1 ddrg0 write: reset: 00000000 = unimplemented figure 20. data direction register g (ddrg) 21-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 328 i/o ports motorola ddrg[2:0] ?data direction register g bits these read/write bits control port g data direction. reset clears ddrg[2:0], configuring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note: avoid glitches on port g pins by writing to the port g data register before changing data direction register g bits from 0 to 1. figure 21 shows the port g i/o logic. when bit ddrgx is a logic one, reading address $000a reads the ptgx data latch. when bit ddrgx is a logic zero, reading address $000a reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data. figure 21. port g i/o circuit read ddrg ($000e) write ddrg ($000e) reset write ptg ($000a) read ptg ($000a) ptgx ddrgx ptgx internal data bus 22-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port h MC68HC08AZ32 motorola i/o ports 329 port h port h is a 2-bit general-purpose bidirectional i/o port. port h data register (pth) the port h data register contains a data latch for each of the two port h pins. pth[1:0] ?port h data bits these read/write bits are software-programmable. data direction of each bit is under the control of the corresponding bit in data direction register h. reset has no effect on port g data. kbd[4:3] ?keyboard inputs the keyboard interrupt enable bits, kbie[4:3], in the keyboard interrupt control register (kbicr), enable the port h pins as external interrupt pins. see keyboard module (kb) on page 299 data direction register h (ddrh) data direction register h determines whether each port h pin is an input or an output. writing a logic one to a ddrh bit enables the output buffer for the corresponding port h pin; a logic zero disables the output buffer. bit 7 654321 bit 0 pth $000b read: 00000 pth1 pth0 write: reset: unaffected by reset alternate function kbd4 kbd3 = unimplemented figure 22. port h data register (pth) bit 7 654321 bit 0 ddrh $000f read: 000000 ddrh1 ddrh0 write: reset: 00000000 = unimplemented figure 23. data direction register h (ddrh) 23-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC08AZ32 330 i/o ports motorola ddrh[1:0] ?data direction register h bits these read/write bits control port h data direction. reset clears ddrh[1:0], configuring all port h pins as inputs. 1 = corresponding port h pin configured as output 0 = corresponding port h pin configured as input note: avoid glitches on port h pins by writing to the port h data register before changing data direction register h bits from 0 to 1. figure 24 shows the port h i/o logic. when bit ddrhx is a logic one, reading address $000b reads the pthx data latch. when bit ddrhx is a logic zero, reading address $000b reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data. figure 24. port h i/o circuit read ddrh ($000e) write ddrh ($000e) reset write pth ($000a) read pth ($000a) ptgx ddrhx pthx internal data bus 24-io f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola mscan08 controller (mscan08) 331 mscan08 controller (mscan08) mscan08 contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 message storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 receive structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 transmit structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 interrupt acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 mscan08 internal sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 soft reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 cpu wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 programmable wake-up function . . . . . . . . . . . . . . . . . . . . . . . . . 350 timer link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 clock system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 programmer? model of message storage . . . . . . . . . . . . . . . . . . . . 355 message buffer outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 identifier registers (idrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 data length register (dlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 data segment registers (dsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . 358 transmit buffer priority registers (tbpr) . . . . . . . . . . . . . . . . . . . 359 programmer? model of control registers . . . . . . . . . . . . . . . . . . . . . 360 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 mscan08 module control register (cmcr0) . . . . . . . . . . . . . . . . 361 mscan08 module control register (cmcr1) . . . . . . . . . . . . . . . . 363 mscan08 bus timing register 0 (cbtr0) . . . . . . . . . . . . . . . . . . . 364 1-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 332 mscan08 controller (mscan08) motorola mscan08 bus timing register 1 (cbtr1) . . . . . . . . . . . . . . . . . . . 365 mscan08 receiver flag register (crflg). . . . . . . . . . . . . . . . . . . 366 mscan08 receiver interrupt enable register (crier) . . . . . . . . 369 mscan08 transmitter flag register (ctflg) . . . . . . . . . . . . . . . 370 mscan08 transmitter control register (ctcr) . . . . . . . . . . . . . 371 mscan08 identifier acceptance control register (cidac) . . . . . 372 mscan08 receive error counter (crxerr) . . . . . . . . . . . . . . . 373 mscan08 transmit error counter (ctxerr) . . . . . . . . . . . . . . . 374 mscan08 identifier acceptance registers (cidar0-3) . . . . . . . . 374 mscan08 identifier mask registers (cidmr0-3). . . . . . . . . . . . . 375 introduction the mscan08 is the specific implementation of the motorola scalable can (mscan) concept targeted for the motorola m68hc08 microcontroller family. the module is a communication controller implementing the can 2.0 a/b protocol as defined in the bosch specification dated september 1991. the can protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. mscan08 utilizes an advanced buffer arrangement resulting in a predictable real-time behaviour and simplifies the application software. 2-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) features MC68HC08AZ32 motorola mscan08 controller (mscan08) 333 features the basic features of the mscan08 are as follows: modular architecture implementation of the can protocol ?version 2.0a/b standard and extended data frames. 0 - 8 bytes data length. programmable bit rate up to 1 mbps 1 . support for remote frames. double buffered receive storage scheme. triple buffered transmit storage scheme with internal prioritization using a ?ocal priority?concept. flexible maskable identifier filter supports alternatively one full size extended identifier filter or two 16 bit filters or four 8 bit filters. programmable wake-up functionality with integrated low-pass filter. programmable loop-back mode supports self-test operation. separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus-off). programmable mscan08 clock source either cpu bus clock or crystal oscillator output. programmable link to on-chip timer interface module (tim) for time-stamping and network synchronization. low power sleep mode. 1. depending on the actual bit timing and the clock jitter of the pll. 3-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 334 mscan08 controller (mscan08) motorola external pins the mscan08 uses 2 external pins, 1 input (rxcan) and 1 output (txcan). the txcan output pin represents the logic level on the can: ??is for a dominant state, and ??is for a recessive state. a typical can system with mscan08 is shown in figure 1 below. figure 1. the can system c a n - bus can controller (mscan08) transceiver can station 1 can station 2 ........ can station n can_l can_h txcan rxcan mcu 4-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 335 each can station is physically connected to the can bus lines through a transceiver chip. the transceiver is capable of driving the large current needed for the can and has current protection, against defected can or defected stations. message storage mscan08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. background modern application layer software is built under two fundamental assumptions: 1. any can node is able to send out a stream of scheduled messages without releasing the bus between two messages. such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. the internal message queue within any can node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. above behaviour can not be achieved with a single transmit buffer. that buffer must be reloaded right after the previous message has been sent. this loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (ifs) in order to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message sending and as such reduces the reactiveness requirements on the cpu. problems may arise if the sending of a message would be finished just while the cpu re-loads the second buffer, no buffer would then be ready for transmission and the bus would be released. 5-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 336 mscan08 controller (mscan08) motorola at least three transmit buffers are required to meet the first of above requirements under all circumstances. the mscan08 has three transmit buffers. the second requirement calls for some sort of internal prioritization which the mscan08 implements with the ?ocal priority?concept described below. receive structures the received messages are stored in a two stage input fifo. the two message buffers are mapped using a ?ing pong?arrangement into a single memory area (see figure 2 ). while the background receive buffer (rxbg) is exclusively associated to the mscan08, the foreground receive buffer (rxfg) is addressable by the cpu08. this scheme simplifies the handler software as only one address area is applicable for the receive process. both buffers have a size of 13 byte to store the can control bits, the identifier (standard or extended) and the data content (for details see programmer? model of message storage on page 355). the receiver full flag (rxf) in the mscan08 receiver flag register (crflg) (see mscan08 receiver flag register (crflg) on page 366) signals the status of the foreground receive buffer. when the buffer contains a correctly received message with matching identifier this flag is set. after the mscan08 successfully received a message into the background buffer it copies the content of rxbg into rxfg 1 , sets the rxf flag, and emits a receive interrupt to the cpu 2 . a new message - which may follow immediately after the ifs field of the can frame - will be received into rxbg. the user? receive handler has to read the received message from rxfg and to reset the rxf flag in order to acknowledge the interrupt and to release the foreground buffer. 1. only if the rxf ?g is not set. 2. the receive interrupt will occur only if not masked. a polling scheme can be applied on rxf also. 6-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 337 an overrun conditions occurs when both, the foreground and the background receive message buffers are filled with correctly received messages and a further message is being received from the bus. the latter message will be discarded and an error interrupt with overrun indication will occur if enabled. the over-writing of the background buffer is independent of the identifier filter function. while in the overrun situation, the mscan08 will stay synchronized to the can bus and is able to transmit messages but will discard all incoming messages. 7-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 338 mscan08 controller (mscan08) motorola note: mscan08 will receive its own messages into the background receive buffer rxbg, but will not overwrite rxfg, and will not emit a receive interrupt, or acknowledge (ack its own messages on the can bus. the figure 2. user model for message buffer organization rxfg rxbg tx0 can receive / transmit engine cpu08 memory mapped i/o rxf txe prio tx1 txe prio tx2 txe prio mscan08 cpu08 ibus 8-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 339 exception to this rule is that when in loop-back mode mscan08 will treat its own messages exactly like all other incoming messages. transmit structures the mscan08 has a triple transmit buffer scheme in order to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. the three buffers are arranged as shown in figure 2 . all three buffers have a 13 byte data structure similar to the outline of the receive buffers (see programmer? model of message storage on page 355). an additional transmit buffer priority register (tbpr) contains an 8-bit so called ?ocal priority?field (prio) (see transmit buffer priority registers (tbpr) on page 359). in order to transmit a message, the cpu08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (txe) flag in the mscan08 transmitter flag register (ctflg) (see mscan08 transmitter flag register (ctflg) on page 370). the cpu08 then stores the identifier, the control bits and the data content into one of the transmit buffers. finally, the buffer has to be flagged as being ready for transmission by clearing the txe flag. the mscan08 will then schedule the message for transmission and will signal the successful transmission of the buffer by setting the txe flag. a transmit interrupt will be emitted 1 when txe is set and can be used to drive the application software to re-load the buffer. in case more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan08 uses the ?ocal priority?setting of the three buffers for prioritization. for this purpose every transmit buffer has an 8-bit local priority field (prio). the application software sets this field when the message is set up. the local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. the lowest binary value of the prio field is defined to be the highest priority. 1. the transmit interrupt will occur only if not masked. a polling scheme can be applied on txe also. 9-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 340 mscan08 controller (mscan08) motorola the internal scheduling process takes places whenever the mscan08 arbitrates for the bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the application software it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. as messages that are already under transmission can not be aborted, the user has to request the abort by setting the corresponding abort request flag (abtrq) in the transmission control register (ctcr). the mscan08 will then grant the request if possible by setting the corresponding abort request acknowledge (abtak) and the txe flag in order to release the buffer and by emitting a transmit interrupt. the transmit interrupt handler software can tell from the setting of the abtak flag whether the message was actually aborted (abtak=1) or has been sent in the meantime (abtak=0). identifier acceptance filter a very flexible programmable generic identifier acceptance filter has been introduced in order to reduce the cpu interrupt loading. the filter is programmable to operate in three different modes: single identifier acceptance filter to be applied to the full 29 bits of the identifier and to the following bits of the can frame: rtr, ide, srr. this mode implements a single filter for a full length can 2.0b compliant extended identifier. double identifier acceptance filter to be applied to the 11 bits of the identifier and the rtr bit of can 2.0a messages or the 14 most significant bits of the identifier of can 2.0b messages. quadruple identifier acceptance filter to be applied to the first 8 bits of the identifier. this mode implements four independent filters for the first 8 bit of a can 2.0a compliant standard identifier. 10-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) interrupts MC68HC08AZ32 motorola mscan08 controller (mscan08) 341 the identifier acceptance registers (ciar) defines the acceptable pattern of the standard or extended identifier (id10 - id0 or id28 - id0). any of these bits can be marked ?on? care?in the identifier mask register (cimr). figure 3. single 32-bit maskable identifier acceptance filter the background buffer rxbg will be copied into the foreground buffer rxfg and the rxf flag will be set only in case of an accepted identifier (an identifier acceptance filter hit). a hit will also cause a receiver interrupt if enabled. a filter hit is indicated to the application software by a set rxf (receive buffer full flag, see mscan08 receiver flag register (crflg) on page 366) and two bits in the identifier acceptance control register (see mscan08 identifier acceptance control register (cidac) on page 372). these identifier hit flags (idhit1-0) clearly identify the filter section that caused the acceptance. they simplify the application software? task to identify the cause of the receiver interrupt. in case that more than one hit occurs (two or more filters match) the lower hit has priority. interrupts the mscan08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 0 hit) 11-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 342 mscan08 controller (mscan08) motorola details see mscan08 receiver flag register (crflg) on page 366 to mscan08 transmitter control register (ctcr) on page 371): transmit interrupt : at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txe flags of the empty message buffers are set. receive interrupt : a message has been successfully received and loaded into the foreground receive buffer. this interrupt will be emitted immediately after receiving the eof symbol. the rxf flag is set. wake-up interrupt : an activity on the can bus occurred during mscan08 internal sleep mode. figure 4. dual 16-bit maskable acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 0 hit) ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 1 hit) 12-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) interrupts MC68HC08AZ32 motorola mscan08 controller (mscan08) 343 figure 5. quadruple 8-bit maskable acceptance filters ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit) 13-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 344 mscan08 controller (mscan08) motorola error interrupt : an overrun, error or warning condition occurred. the receiver flag register (crflg) will indicate one of the following conditions: overrun: an overrun condition as described in receive structures on page 336, has occurred. receiver warning : the receive error counter has reached the cpu warning limit of 96. transmitter warning : the transmit error counter has reached the cpu warning limit of 96. receiver error passive : the receive error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. transmitter error passive : the transmit error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. bus off : the transmit error counter has exceeded 255 and mscan08 has gone to bus off state. interrupt acknowledge interrupts are directly associated with one or more status flags in either the mscan08 receiver flag register (crflg) or the mscan08 transmitter control register (ctcr). interrupts are pending as long as one of the corresponding flags is set. the flags in above registers must be reset within the interrupt handler in order to handshake the interrupt. the flags are reset through writing a ??to the corresponding bit position. a flag can not be cleared if the respective condition still prevails. caution: bit manipulation instructions ( bset ) shall not be used to clear interrupt flags. the ?r?instruction is the appropriate way to clear selected flags. interrupt vectors the mscan08 supports four interrupt vectors as shown in table 1 . the vector addresses are dependent on the chip integration and to be defined. the relative interrupt priority is also integration dependent and to be defined. 14-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) interrupts MC68HC08AZ32 motorola mscan08 controller (mscan08) 345 table 1. mscan08 interrupt vectors function source local mask global mask wake-up wupif wupie i bit error interrupts rwrnif rwrnie twrnif twrnie rerrif rerrie terrif terrie boffif boffie ovrif ovrie receive rxf rxfie transmit txe0 txeie0 txe1 txeie1 txe2 txeie2 15-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 346 mscan08 controller (mscan08) motorola protocol violation protection the mscan08 will protect the user from accidentally violating the can protocol through programming errors. the protection logic implements the following features: the receive and transmit error counters can not be written or otherwise manipulated. all registers which control the configuration of the mscan08 can not be modified while the mscan08 is on-line. the sftres bit in the mscan08 module control register (see mscan08 module control register (cmcr1) on page 363) serves as a lock to protect the following registers: mscan08 module control register 1 (cmcr1) mscan08 bus timing register 0 and 1 (cbtr0, cbtr1) mscan08 identifier acceptance control register (cidac) mscan08 identifier acceptance registers (cidar0-3) mscan08 identifier mask registers (cidmr0-3) the txcan pin is forced to recessive if the cpu goes into stop mode. 16-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) low power modes MC68HC08AZ32 motorola mscan08 controller (mscan08) 347 low power modes the mscan08 has three modes with reduced power consumption compared to normal mode. in sleep and soft reset mode, power consumption is reduced by stopping all clocks except those to access the registers. in power down mode, all clocks are stopped and no power is consumed. wait and stop instruction put the mcu in low power consumption stand-by mode. table 2 summarizes the combinations of mscan08 and cpu modes. a particular combination of modes is entered for the given settings of the bits slpak and sftres. in sleep and soft reset mode, power consumption of the mscan module is lower than in normal mode. in power down mode, no power is consumed in the module and no registers can be accessed. for all modes, an mscan wake-up interrupt can occur only if slpak = wupie = 1. while the cpu is in wait mode, the mscan08 is operated as in normal mode. table 2. mscan08 vs cpu operating modes mscan mode cpu mode stop wait or run power down slpak = x (1) sftres = x 1. ??means don? care. sleep slpak = 1 sftres = 0 soft reset slpak = 0 sftres = 1 normal slpak = 0 sftres = 0 17-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 348 mscan08 controller (mscan08) motorola mscan08 internal sleep mode the cpu can request the mscan08 to enter the low-power mode by asserting the slprq bit in the module configuration register (see figure 6 ). the time when the mscan08 will then enter sleep mode depends on its current activity: if it is transmitting, it will continue to transmit until there is no more message to be transmitted, and then go into sleep mode if it is receiving, it will wait for the end of this message and then go into sleep mode if it is neither transmitting or receiving, it will immediately go into sleep mode the application software must avoid to set up a transmission (by clearing one or more txe flag(s)) and immediately request sleep mode (by setting slprq). it will then depend on the exact sequence of operations whether the mscan will start transmitting or go into sleep mode directly. during sleep mode the slpak flag is set. the application software should use this flag as a handshake indication for the request to go into sleep mode.when in sleep mode the mscan08 stops its own clocks and the txcan pin will stay in recessive state. the mscan08 will leave sleep mode (wake-up) when bus activity occurs or when the mcu clears the slprq bit. note: the mcu can not clear the slprq bit before the mscan08 is in sleep mode (slpak = 1). 18-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) low power modes MC68HC08AZ32 motorola mscan08 controller (mscan08) 349 soft reset mode in soft reset mode, the mscan08 is stopped. registers can still be accessed. this mode is used to initialize the module configuration, bit timing, and the can message filter. see mscan08 module control register (cmcr0) on page 361, for a complete description of the soft reset mode. power down mode the mscan08 is in power down mode when the cpu is in stop mode. when entering the power down mode, the mscan08 immediately stops all ongoing transmissions and receptions, potentially causing can protocol violations. it is the user? responsibility to take care that the mscan08 is not active when power down mode is entered. the recommended procedure is to bring the mscan08 into sleep mode before the stop instruction is executed. figure 6. sleep request/acknowledge cycle mscan08 sleeping slprq = 1 slpak = 1 mscan08 running slprq = 0 slpak = 0 sleep request slprq = 1 slpak = 0 mcu mscan08 mcu or mscan08 19-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 350 mscan08 controller (mscan08) motorola to protect the can bus system from fatal consequences of violations to the above rule, the mscan08 will drive the txcan pin into recessive state. cpu wait mode the mscan08 module remains active during cpu wait mode. the mscan08 will stay synchronized to the can bus and will generate enabled transmit, receive and error interrupts to the cpu. any such interrupt will bring the mcu out of wait mode. programmable wake-up function the mscan08 can be programmed to apply a low-pass filter function to the rxcan input line while in internal sleep mode (see control bit wupm in mscan08 module control register (cmcr1) on page 363). this feature can be used to protect the mscan08 from wake-up due to short glitches on the can bus lines. such glitches can result from electromagnetic inference within noisy environments. timer link the mscan08 will generate a timer signal whenever a valid frame has been received. because the can specification defines a frame to be valid if no errors occurred before the eof field has been transmitted successfully, the timer signal will be generated right after the eof. a pulse of one bit time is generated. as the mscan08 receiver engine receives also the frames being sent by itself, a timer signal will also be generated after a successful transmission. the previously described timer signal can be routed into the on-chip timer interface module (tim). under the control of the timer link enable (tlnken) bit in the cmcr0 will this signal be connected to the timer n channel m input 1 . after timer n has been programmed to capture rising edge events it can be used to generate 16-bit time stamps which can be stored under software control with the received message. 1. the timer channel being used for the timer link is integration dependent. 20-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) clock system MC68HC08AZ32 motorola mscan08 controller (mscan08) 351 clock system figure 7 shows the structure of the mscan08 clock generation circuitry and its interaction with the clock generation module (cgm). with this flexible clocking scheme the mscan08 is able to handle can bus rates ranging from 10 kbps up to 1 mbps. the clock source flag (clksrc) in the mscan08 module control register (cmcr1) (see mscan08 module control register (cmcr1) on page 363) defines whether the mscan08 is connected to the output of the crystal oscillator or to the pll output. a programmable prescaler is used to generate from the mscan08 clock the time quanta (tq) clock. a time quantum is the atomic unit of time handled by the mscan08. a bit time is subdivided into three segments 1 : figure 7. clocking scheme 1. for further explanation of the under-lying concepts please refer to iso/dis 11519-1, section 10.3. / 2 mscan08 prescaler (1 .. 64) osc cgmxclk / 2 cgmout (to sim) cgm / 2 clksrc mscanclk (2 * bus freq.) bcs time quanta clock pll 21-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 352 mscan08 controller (mscan08) motorola sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segment includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents the phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. the synchronization jump width can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. above parameters can be set by programming the bus timing registers cbtr0-1 (see mscan08 bus timing register 0 (cbtr0) on page 364 and mscan08 bus timing register 1 (cbtr1) on page 365). it is the user? responsibility to make sure that his bit time settings are in compliance with the can standard. figure 8 and table 3 give an overview on the can conforming segment settings and the related parameter values. 22-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) clock system MC68HC08AZ32 motorola mscan08 controller (mscan08) 353 figure 8. segments within the bit time table 3. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchron. jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 sync _seg time segment 1 time seg. 2 1 4 ... 16 2 ... 8 8... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point 23-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 354 mscan08 controller (mscan08) motorola memory map the mscan08 occupies 128 byte in the cpu08 memory space. the absolute mapping is implementation dependent with the base address being a multiple of 128. the background receive buffer can only be read in test mode. $xx00 control registers 9 bytes $xx08 $xx09 reserved 5 bytes $xx0d $xx0e error counters 2 bytes $xx0f $xx10 identifier filter 8 bytes $xx17 $xx18 reserved 40 bytes $xx3f $xx40 receive buffer $xx4f $xx50 transmit buffer 0 $xx5f $xx60 transmit buffer 1 $xx6f $xx70 transmit buffer 2 $xx7f figure 9. mscan08 memory map 24-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 355 programmer?s model of message storage the following section details the organisation of the receive and transmit message buffers and the associated control registers. for reasons of programmer interface simplification the receive and transmit message buffers have the same outline. each message buffer allocates 16 byte in the memory map containing a 13 byte data structure. an additional transmit buffer priority register (tbpr) is defined for the transmit buffers. message buffer outline figure 11 shows the common 13 byte data structure of receive and transmit buffers for extended identifiers. the mapping of standard identifiers into the idr registers is shown in figure 12 . all bits of the 13 byte data structure are undefined out of reset. addr register name xxb0 identifier register 0 xxb1 identifier register 1 xxb2 identifier register 2 xxb3 identifier register 3 xxb4 data segment register 0 xxb5 data segment register 1 xxb6 data segment register 2 xxb7 data segment register 3 xxb8 data segment register 4 xxb9 data segment register 5 xxba data segment register 6 xxbb data segment register 7 xxbc data length register xxbd transmit buffer priority register (1) 1. not applicable for receive buffers xxbe unused xxbf unused figure 10. message buffer organisation 25-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 356 mscan08 controller (mscan08) motorola identifier registers (idrn) the identifiers consist of either 11 bits (id10?d0) for the standard, or 29 bits (id28?d0) for the extended format. id10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. the priority of an identifier is defined to be highest for the smallest binary number. addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxb0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w $xxb1 idr1 r id20 id19 id18 srr (1) ide (1) id17 id16 id15 w $xxb2 idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w $xxb3 idr3 r id6 id5 id4 id3 id2 id1 id0 rtr w $xxb4 dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxb5 dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxb6 dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxb7 dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxb8 dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxb9 dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxba dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxbb dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w $xxbc dlr r dlc3 dlc2 dlc1 dlc0 w figure 11. receive/transmit message buffer extended identifier 26-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 357 srr ?substitute remote request this fixed recessive bit is used only in extended format. it must be set to 1 by the user for transmission buffers and will be stored as received on the can bus for receive buffers. ide ?id extended this flag indicates whether the extended or standard identifier format is applied in this buffer. in case of a receive buffer the flag is set as being received and indicates to the cpu how to process the buffer identifier registers. in case of a transmit buffer the flag indicates to the mscan08 what type of identifier to send. 1 = extended format (29 bit) 0 = standard format (11 bit) rtr ?remote transmission request this flag reflects the status of the remote transmission request bit in the can frame. in case of a receive buffer it indicates the status of the received frame and allows to support the transmission of an answering frame in software. in case of a transmit buffer this flag defines the setting of the rtr bit to be sent. 1 = remote frame 0 = data frame addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxb0 idr0 r id10 id9 id8 id7 id6 id5 id4 id3 w $xxb1 idr1 r id2 id1 id0 rtr ide(0) w $xxb2 idr2 r w $xxb3 idr3 r w figure 12. standard identifier mapping registers 27-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 358 mscan08 controller (mscan08) motorola data length register (dlr) this register keeps the data length field of the can frame. dlc3?lc0 ?data length code bits the data length code contains the number of bytes (data byte count) of the respective message. at transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 4 shows the effect of setting the dlc bits. data segment registers (dsrn) the eight data segment registers contain the data to be transmitted or being received. the number of bytes to be transmitted or being received is determined by the data length code in the corresponding dlr. table 4. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008 28-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of message storage MC68HC08AZ32 motorola mscan08 controller (mscan08) 359 transmit buffer priority registers (tbpr) prio7?rio0?local priority this field defines the local priority of the associated message buffer. the local priority is used for the internal prioritization process of the mscan08 and is defined to be highest for the smallest binary number. the mscan08 implements the following internal prioritization mechanism: all transmission buffers with a cleared txe flag participate in the prioritization right before the sof (start of frame) is sent. the transmission buffer with the lowest local priority field wins the prioritization. in case of more than one buffer having the same lowest priority the message buffer with the lower index number wins. caution: to ensure data integrity, no registers of the transmit buffers shall be written while the associated txe flag is cleared. also, no registers of the receive buffer shall be read while the rxf flag is cleared. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbpr r prio7 prio5 prio5 prio4 prio3 prio2 prio1 prio0 $xxbd w reset uuuuuuuu figure 13.transmit buffer priority register (tbpr) 29-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 360 mscan08 controller (mscan08) motorola programmer?s model of control registers overview the programmer? model has been laid out for maximum simplicity and efficiency. the figure 14 gives an overview on the control register block of the mscan08: addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xx00 cmcr0 r 0 0 0 synch tlnken slpak slprq sftres w $xx01 cmcr1 r00000 loopb wupm clksrc w * $xx02 cbtr0 r w sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 $xx03 cbtr1 r w * samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 $xx04 crflg r wupif rwrnif twrnif rerrif terrif boffif ovrif rxf w $xx05 crier r wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie w $xx06 ctflg r0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 w $xx07 ctcr r0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 w $xx08 cidac r0 0 idam1 idam0 0 0 idhit1 idhit0 w * $xx09-$ xx0d reserved r w $xx0e crxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w $xx0f ctxerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w $xx10 cidar0 r w * ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx11 cidar1 r w * ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx12 cidar2 r w * ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx13 cidar3 r w * ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 = unimplemented figure 14. mscan08 control register structure 30-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 361 mscan08 module control register (cmcr0) . synch ?synchronized status this bit indicates whether the mscan08 is synchronized to the can bus and as such can participate in the communication process. 1 = mscan08 is synchronized to the can bus 0 = mscan08 is not synchronized to the can bus tlnken ?timer enable this flag is used to establish a link between the mscan08 and the on-chip timer (see timer link on page 350). 1 = the mscan08 timer signal output is connected to the timer. 0 = no connection. $xx14 cidmr0 r w * am7 am6 am5 am4 am3 am2 am1 am0 $xx15 cidmr1 r w * am7 am6 am5 am4 am3 am2 am1 am0 $xx16 cidmr2 r w * am7 am6 am5 am4 am3 am2 am1 am0 $xx17 cidmr3 r w * am7 am6 am5 am4 am3 am2 am1 am0 = unimplemented addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 14. mscan08 control register structure (continued) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmcr0 r 0 0 0 synch tlnken slpak slprq sftres $xx00 w reset 00000001 = unimplemented figure 15. module control register 0 (cmcr0) 31-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 362 mscan08 controller (mscan08) motorola slpak ?sleep mode acknowledge this flag indicates whether the mscan08 is in module internal sleep mode. it shall be used as a handshake for the sleep mode request (see mscan08 internal sleep mode on page 348). 1 = sleep ?the mscan08 is in internal sleep mode. 0 = wake-up ?the mscan08 will function normally. slprq ?sleep request, go to internal sleep mode this flag allows to request the mscan08 to go into an internal power-saving mode (see mscan08 internal sleep mode on page 348). 1 = sleep ?the mscan08 will go into internal sleep mode if and as long as there is no activity on the bus. 0 = wake-up ?the mscan08 will function normally. if slprq is cleared by the cpu then the mscan08 will wake up, but will not issue a wake-up interrupt. sftres ?soft reset when this bit is set by the cpu, the mscan08 immediately enters the soft reset state. any ongoing transmission or reception is aborted and synchronization to the bus is lost. the following registers will go into the same state as out of hard reset: cmcr0, crflg, crier, ctflg, ctcr. the registers cmcr1, cbtr0, cbtr1, cidac, cidar0-3, cidmr0-3 can only be written by the cpu when the mscan08 is in soft reset state. the values of the error counters are not affected by soft reset. when this bit is cleared by the cpu, the mscan08 will try to synchronize to the can bus: if the mscan08 is not in bus-off state it will be synchronized after 11 recessive bits on the bus; if the mscan08 is in bus-off state it continues to wait for 128 occurrences of 11 recessive bits. 1 = mscan08 in soft reset state. 0 = normal operation 32-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 363 mscan08 module control register (cmcr1) . loopb ?loop back self test mode when this bit is set the mscan08 performs an internal loop back which can be used for self test operation: the bit stream output of the transmitter is fed back to the receiver. the rxcan input pin is ignored and the txcan output goes to the recessive state (1). note that in this state the mscan08 ignores the ack bit to insure proper reception of its own message and will treat messages being received while in transmission as received messages from remote nodes. 1 = activate loop back self test mode 0 = normal operation wupm ?wake-up mode this flag defines whether the integrated low-pass filter is applied to protect the mscan08 from spurious wake-ups (see programmable wake-up function on page 350). 1 = mscan08 will wake up the cpu only in case of dominant pulse on the bus which has a length of at least approximately t wup . 0 = mscan08 will wake up the cpu after any recessive to dominant edge on the can bus. clksrc ?clock source this flag defines which clock source the mscan08 module is driven from (see clock system on page 351). 1 = the mscan08 clock source is cgmout (see figure 7 ). 0 = the mscan08 clock source is cgmxclk/2 (see figure 7 ). note: the cmcr1 register can only be written if the sftres bit in the mscan08 module control register is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmcr1 r 00000 loopb wupm clksrc $xx01 w reset 00000000 = unimplemented figure 16. module control register 1 (cmcr1) 33-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 364 mscan08 controller (mscan08) motorola mscan08 bus timing register 0 (cbtr0) sjw1, sjw0 ?synchronization jump width the synchronization jump width defines the maximum number of time quanta (tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see table 5 ). brp5?rp0 ?baud rate prescaler these bits determine the time quanta (tq) clock, which is used to build up the individual bit timing, according to table 6 . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cbtr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 $xx02 w reset 00000000 figure 17. bus timing register 0 table 5. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 6. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 0000001 0000012 0000103 0000114 ::::::: ::::::: 11111164 34-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 365 note: the cbtr0 register can only be written if the sftres bit in the mscan08 module control register is set. mscan08 bus timing register 1 (cbtr1) . samp ?sampling this bit determines the number of samples of the serial bus to be taken per bit time. if set three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. for higher bit rates samp should be cleared, which means that only one sample will be taken per bit. 1 = three samples per bit. 0 = one sample per bit. tseg22?seg10 ?time segment time segments within the bit time fix the number of clock cycles per bit time, and the location of the sample point. time segment 1 (tseg1) and time segment 2 (tseg2) are programmable as shown in table 8 . the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown above). note: the cbtr1 register can only be written if the sftres bit in the mscan08 module control register is set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cbtr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 $xx03 w reset 00000000 figure 18. bus timing register 1 35-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 366 mscan08 controller (mscan08) motorola . mscan08 receiver flag register (crflg) all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. a flag can only be cleared when the condition which caused the setting is no more valid. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the crier register. a hard or soft reset will clear the register. table 7. time segment syntax sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode will transfer a new value to the can bus at this point. sample point a node in receive mode will sample the bus at this point. if the three samples per bit option is selected then this point marks the position of the third sample. table 8. time segment values tseg 13 tseg 12 tseg 11 tseg 10 time segment 1 tseg 22 tseg 21 tseg 20 time segment 2 0 0 0 0 1 tq clock cycle 0 0 0 1 tq clock cycle 0 0 0 1 2 tq clock cycles 0 0 1 2 tq clock cycles 0 0 1 0 3 tq clock cycles . . . . 0 0 1 1 4 tq clock cycles . . . . . . . . . 1 1 1 8 tq clock cycles .... . 1 1 1 1 16 tq clock cycles bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crflg r wupif rwrnif twrnif rerrif terrif boffif ovrif rxf $xx04 w reset 00000000 figure 19. receiver flag register 36-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 367 wupif ?wake-up interrupt flag if the mscan08 detects bus activity whilst it is asleep, it clears the slpak bit in the cmcr0 register; the wupif bit will then be set. if not masked, a wake-up interrupt is pending while this flag is set. 1 = mscan08 has detected activity on the bus and requested wake-up. 0 = no wake-up activity has been observed while in sleep mode. rwrnif ?receiver warning interrupt flag this bit will be set when the mscan08 went into warning status due to the receive error counter being in the range of 96 to 127. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into receiver warning status. 0 = no receiver warning status has been reached. twrnif ?transmitter warning interrupt flag this bit will be set when the mscan08 went into warning status due to the transmit error counter being in the range of 96 to 127. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into transmitter warning status. 0 = no transmitter warning status has been reached. rerrif ?receiver error passive interrupt flag this bit will be set when the mscan08 went into error passive status due to the receive error counter exceeded 127. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into receiver error passive status. 0 = no receiver error passive status has been reached. terrif ?transmitter error passive interrupt flag this bit will be set when the mscan08 went into error passive status due to the transmit error counter exceeded 127. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into transmitter error passive status. 0 = no transmitter error passive status has been reached. 37-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 368 mscan08 controller (mscan08) motorola boffif ?bus-off interrupt flag this bit will be set when the mscan08 went into bus-off status, due to the transmit error counter exceeded 255. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into bus-off status. 0 = no bus-off status has been reached. ovrif ?overrun interrupt flag this bit will be set when a data overrun condition occurred. if not masked, an error interrupt is pending while this flag is set. 1 = a data overrun has been detected. 0 = no data overrun has occurred. rxf ?receive buffer full the rxf flag is set by the mscan08 when a new message is available in the foreground receive buffer. this flag indicates whether the buffer is loaded with a correctly received message. after the cpu has read that message from the receive buffer the rxf flag must be handshaken to release the buffer. a set rxf flag prohibits the exchange of the background receive buffer into the foreground buffer. in that case the mscan08 will signal an overload condition. if not masked, a receive interrupt is pending while this flag is set. 1 = the receive buffer is full. a new message is available. 0 = the receive buffer is released (not full). note: the crflg register is held in the reset state when the sftres bit in cmcr0 is set. 38-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 369 mscan08 receiver interrupt enable register (crier) wupie ?wake-up interrupt enable 1 = a wake-up event will result in a wake-up interrupt. 0 = no interrupt will be generated from this event. rwrnie ?receiver warning interrupt enable 1 = a receiver warning status event will result in an error interrupt. 0 = no interrupt will be generated from this event. twrnie ?transmitter warning interrupt enable 1 = a transmitter warning status event will result in an error interrupt. 0 = no interrupt will be generated from this event. rerrie ?receiver error passive interrupt enable 1 = a receiver error passive status event will result in an error interrupt. 0 = no interrupt will be generated from this event. terrie ?transmitter error passive interrupt enable 1 = a transmitter error passive status event will result in an error interrupt. 0 = no interrupt will be generated from this event. boffie ?bus-off interrupt enable 1 = a bus-off event will result in an error interrupt. 0 = no interrupt will be generated from this event. ovrie ?overrun interrupt enable 1 = an overrun event will result in an error interrupt. 0 = no interrupt will be generated from this event. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crier r wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie $xx05 w reset 00000000 figure 20. receiver interrupt enable register 39-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 370 mscan08 controller (mscan08) motorola rxfie ?receiver full interrupt enable 1 = a receive buffer full (successful message reception) event will result in a receive interrupt. 0 = no interrupt will be generated from this event. note: the crier register is held in the reset state when the sftres bit in cmcr0 is set. mscan08 transmitter flag register (ctflg) all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the ctcr register. a hard or soft reset will clear the register. abtak2?btak0 ?abort acknowledge this flag acknowledges that a message has been aborted due to a pending abort request from the cpu. after a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent in the meantime. the flag is reset implicitly whenever the associated txe flag is set to 0. 1 = the message has been aborted. 0 = the massage has not been aborted, thus has been sent out. txe2?xe0 ?ransmitter buffer empty this flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. the cpu must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. the mscan08 will set the flag after the message has been sent successfully. the flag will also be set by the mscan08 when the transmission request was bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctflg r 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 $xx06 w reset 00000111 = unimplemented figure 21. transmitter flag register 40-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 371 successfully aborted due to a pending abort request (see mscan08 transmitter control register (ctcr) on page 371). if not masked, a transmit interrupt is pending while this flag is set. a reset of this ?g will also reset the abort acknowledge (abtak, see above) and the abort request (abtrq) (see mscan08 trans- mitter control register (ctcr) on page 371), ?gs of the particular buffer. 1 = the associated message buffer is empty (not scheduled). 0 = the associated message buffer is full (loaded with a message due for transmission). note: the ctflg register is held in the reset state when the sftres bit in cmcr0 is set. mscan08 transmitter control register (ctcr) abtrq2?btrq0 ?abort request the cpu sets this bit to request that an already scheduled message buffer (txe = 0) shall be aborted. the mscan08 will grant the request when the message is not already under transmission. when a message is aborted the associated txe and the abort acknowledge flag abtak) (see mscan08 transmitter flag register (ctflg) on page 370), will be set and an txe interrupt will occur if enabled. the cpu can not reset abtrqx. abtrqx is reset implicitly whenever the associated txe flag is set. 1 = abort request pending. 0 = no abort request. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctcr r 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 $xx07 w reset 00000000 = unimplemented table 9. transmitter control register 41-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 372 mscan08 controller (mscan08) motorola txeie2?xeie0 ?transmitter empty interrupt enable 1 = a transmitter empty (transmit buffer available for transmission) event will result in a transmitter empty interrupt. 0 = no interrupt will be generated from this event. note: the ctcr register is held in the reset state when the sftres bit in cmcr0 is set. mscan08 identifier acceptance control register (cidac) idam1?dam0?identifier acceptance mode the cpu sets these flags to define the identifier acceptance filter organization (see identifier acceptance filter on page 340). table 10 summarizes the different settings. in ?ilter closed?mode no messages will be accepted such that the foreground buffer will never be reloaded. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cidac r 0 0 idam1 idam0 0 0 idhit1 idhit0 $xx08 w reset 00000000 = unimplemented figure 22. identifier acceptance control register table 10. identi?r acceptance mode settings idam1 idam0 identifier acceptance mode 0 0 single 32 bit acceptance filter 0 1 two 16 bit acceptance filter 1 0 four 8 bit acceptance filters 1 1 filter closed 42-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 373 idhit1?dhit0?identifier acceptance hit indicator the mscan08 sets these flags to indicate an identifier acceptance hit (see identifier acceptance filter on page 340). table 11 summarizes the different settings. the idhit indicators are always related to the message in the foreground buffer. when a message gets copied from the background to the foreground buffer the indicators are updated as well. note: the cidac register can only be written if the sftres bit in the mscan08 module control register is set. mscan08 receive error counter (crxerr) this register reflects the status of the mscan08 receive error counter. the register is read only. table 11. identi?r acceptance hit indication idhit1 idhit0 identifier acceptance hit 0 0 filter 0 hit 0 1 filter 1 hit 1 0 filter 2 hit 1 1 filter 3 hit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 $xx0e w reset 00000000 = unimplemented figure 23. receive error counter 43-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 374 mscan08 controller (mscan08) motorola mscan08 transmit error counter (ctxerr) this register reflects the status of the mscan08 transmit error counter. the register is read only. note: both error counters may only be read when in sleep or soft reset mode. mscan08 identifier acceptance registers (cidar0-3) on reception each message is written into the background receive buffer. the cpu is only signalled to read the message however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). the acceptance registers of the mscan08 are applied on the idr0 to idr3 registers of incoming messages in a bit by bit manner. for extended identifiers all four acceptance and mask registers are applied. for standard identifiers only the first two (idar0, idar1) are applied. in the latter case it is required to program the mask register cidmr1 in the three last bits (ac2 - ac0) to ?on? care? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctxerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 $xx0f w reset 00000000 = unimplemented figure 24. transmit error counter 44-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) programmer? model of control registers MC68HC08AZ32 motorola mscan08 controller (mscan08) 375 ac7?c0 ?acceptance code bits ac7?c0 comprise a user defined sequence of bits with which the corresponding bits of the related identifier register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identifier mask register. note: the cidar0-3 registers can only be written if the sftres bit in the mscan08 module control register is set mscan08 identifier mask registers (cidmr0-3) the identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cidar0 $xx10 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w cidar1 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx11 w cidar2 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx12 w cidar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $xx13 w reset uuuuuuuu u = unaffected figure 25. identifier acceptance registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cidmr0 $xx14 r am7 am6 am5 am4 am3 am2 am1 am0 w cidmr1 r am7 am6 am5 am4 am3 am2 am1 am0 $xx15 w cidmr2 r am7 am6 am5 am4 am3 am2 am1 am0 $xx16 w cidmr3 r am7 am6 am5 am4 am3 am2 am1 am0 $xx17 w reset uuuuuuuu u = unaffected figure 26. identifier mask registers 45-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mscan08 controller (mscan08) MC68HC08AZ32 376 mscan08 controller (mscan08) motorola am7?m0 ?acceptance mask bits if a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit, before a match will be detected. the message will be accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted. bit description: 1 = ignore corresponding acceptance code register bit. 0 = match corresponding acceptance code register and identifier bits. note: the cidmr0-3 registers can only be written if the sftres bit in the mscan08 module control register is set 46-can f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola specifications 377 specifications specifications contents maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 380 control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 5.0 vdc ?0.5v serial peripheral interface (spi) timing . . . . . . . . . . 383 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 cgm component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 cgm acquisition/lock time information. . . . . . . . . . . . . . . . . . . . . . 387 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 mechanical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 64-pin quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 1-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 378 specifications motorola maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate at the maximum ratings. refer to 5.0 volt dc electrical characteristics on page 380 for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating symbol value unit supply voltage v dd ?.3 to +6.0 v input voltage v in v ss ?.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?5 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma reset irq input voltage v hi v dd +2 to v dd + 4 v note: voltages are referenced to v ss . 2-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications functional operating range MC68HC08AZ32 motorola specifications 379 functional operating range note: for applications which use the lvi, motorola guarantee the functionality of the device down to the lvi trip point (v lvii ). thermal characteristics notes: 1. power dissipation is a function of temperature. 2. k is a constant unique to the device. k can be determined from a known t a and measured p d. with this value of k, p d , and t j can be determined for any value of t a . rating symbol value unit operating temperature range (1) 1. t a (max) = 125 c for part suffix mfu 105 c for part suffix vfu 85 c for part suffix cfu t a ?0 to t a (max) c operating voltage range v dd 5.0 0.5v v characteristic symbol value unit thermal resistance qfp (64 pins) q ja 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (see note 1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c w constant (see note 2) k p d x (t a + 273 c) + (p d 2 x q ja ) w/ c average junction temperature t j t a = p d x q ja c 3-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 380 specifications motorola 5.0 volt dc electrical characteristics characteristic symbol min max unit output high voltage (i load = ?.0 ma) all ports v oh v dd ?.8 v (i load = ?.0 ma) all ports v dd ?.5 v total source current i ohtot ?0ma output low voltage (i load = 1.6 ma) all ports v ol 0.4 v (i load = 10.0 ma) all ports 1.5 v total sink current i oltot ?5ma input high voltage all ports, irq s , reset, osc1 v ih 0.7 x v dd v dd v input low voltage all ports, irq s , reset, osc1 v il v ss 0.3 x v dd v v dd + v dda supply current run (see note 3)(see note 10) wait (see note 4)(see note 10) stop (see note 5) 25 c ?0 c to +125 c 25 c with lvi enabled ?0 c to +125 c with lvi enabled i dd 30 14 50 100 400 500 ma ma m a m a m a m a i/o ports hi-z leakage current i l 1 m a input current i in 1 m a capacitance ports (as input or output) c out c in 12 8 pf low-voltage reset inhibit (trip) (recover) v lv i 4.0 4.4 v por rearm voltage (see note 6) v por 0 200 mv por reset voltage (see note 7) v porrst 0 800 mv por rise time ramp rate (see note 8) r por 0.02 v/ms high cop disable voltage (see note 9) v hi v dd v dd + 2 v 4-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications control timing MC68HC08AZ32 motorola specifications 381 control timing 1.v dd = 5.0 vdc 0.5v, v ss = 0 vdc, t a = ?0 c to t a (max) , unless otherwise noted. 2.typical values reflect average measurements at midpoint of voltage range, 25 c only. 3.run (operating) i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capaci- tance linearly affects run i dd . measured with all modules enabled. 4.wait i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 vdc from rail. no dc loads. less than 100 pf on all outputs, c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with all modules enabled. 5.stop i dd measured with osc1 = v ss . 6.maximum is highest voltage that por is guaranteed. 7.maximum is highest voltage that por is possible. 8.if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 9.see computer operating properly module (cop) on page 143 . 10.although i dd is proportional to bus frequency, a current of several ma is present even at very low frequencies. characteristic symbol min max unit bus operating frequency (4.5?.5 v ?v dd only) f bus 8.4 mhz reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 t cyc irq interrupt pulse period t ilil note 3 t cyc eeprom programming time per byte t eepgm 10 ms eeprom erasing time per byte t ebyte 10 ms eeprom erasing time per block t eblock 10 ms eeprom erasing time per bulk t ebulk 10 ms eeprom programming voltage discharge period t eefpv 100 200 m s 16-bit timer (see note 2) input capture pulse width (see note 3) input capture period t th, t tl t tltl 2 note 4 t cyc mscan wake-up filter pulse width (see note 5) t wup 25 m s 1.v dd = 5.0 vdc 0.5v, v ss = 0 vdc, t a = ?0 c to t a (max) , unless otherwise noted. 2.the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3.refer to mode, edge, and level selection on page 276 and supporting note. 4.the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execute the capture interrupt service routine plus tbd t cyc . 5. the minimum pulse width to wake up the mscan module is guaranteed by design but not tested. 5-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 382 specifications motorola adc characteristics characteristic min max unit comments resolution 8 8 bits absolute accuracy (v refl = 0 v, v dda = v refh = 5 v 0.5v) ? +1 lsb includes quantization conversion range (see note 1) v refl v refh vv refl = v ssa power-up time 16 17 m s conversion time period input leakage (see note 3) ports b and d 1 m a conversion time 16 17 adc clock cycles includes sampling time monotonicity inherent within total error zero input reading 00 01 hex v in = v refl full-scale reading fe ff hex v in = v refh sample time (see note 2) 5 adc clock cycles input capacitance 8 pf not tested adc internal clock 500 k 1.048 m hz tested only at 1 mhz analog input voltage v refl v refh v 1.v dd = 5.0 vdc 0.5v, v ss = 0 vdc, v dda /v ddaref = 5.0 vdc 0.5v, v ssa = 0 vdc, v refh = 5.0 vdc 0.5v 2.source impedances greater than 10 k w adversely affect internal rc charging time during input sampling. 3.the external system error caused by input leakage current is approximately equal to the product of r source and input current. 6-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications 5.0 vdc 0.5v serial peripheral interface (spi) timing MC68HC08AZ32 motorola specifications 383 5.0 vdc 0.5v serial peripheral interface (spi) timing num characteristic symbol min max unit operating frequency (see note 3) master slave f bus( m ) f bus( s ) f bus /128 dc f bus /2 f bus mhz 1 cycle time master slave t cyc( m ) t cyc( s ) 2 1 128 t cyc 2 enable lead time t lead 15 ns 3 enable lag time t lag 15 ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 100 50 ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 100 50 ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ns 8 access time, slave (see note 4) cpha = 0 cpha = 1 t a(cp0) t a(cp1) 0 0 40 20 ns 9 slave disable time (hold time to high-impedance state) (see note 5) t dis ?5ns 10 data valid time after enable edge (see note 6) master slave t v(m) t v(s) 10 40 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 5 ns 1. all timing is shown with respect to 30% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. 2. item numbers refer to dimensions in figure 1 and figure 2 . 3. f bus = the currently active bus frequency for the microcontroller. 4. time to data active from high-impedance state. 5. hold time to high-impedance state. 6. with 100 pf on all spi pins 7-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 384 specifications motorola figure 1. spi master timing diagram note ss pin of master held high msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 12 13 bit 6? lsb in master msb out bit 6? master lsb out 10 (ref) 13 11 10 12 11 (ref) 7 6 note ss pin of master held high msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 13 bit 6? lsb in master msb out bit 6? master lsb out 10 (ref) 13 11 10 12 11 7 6 12 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 note: this first clock edge is generated internally, but is not seen at the sck pin. note: this last clock edge is generated internally, but is not seen at the sck pin. 8-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications 5.0 vdc 0.5v serial peripheral interface (spi) timing MC68HC08AZ32 motorola specifications 385 figure 2. spi slave timing diagram note: not defined but normally msb of character just received. slave ss input sck (cpol = 0) input sck (cpol = 1) input miso input mosi output 4 5 5 1 13 12 4 13 msb in bit 6? 8 6 10 11 11 12 note slave lsb out 9 3 lsb in 2 7 bit 6? msb out note: not defined but normally lsb of character previously transmitted. slave ss input sck (cpol = 0) input sck (cpol = 1) input miso output mosi input 4 5 5 1 13 12 4 13 msb in bit 6? 8 6 10 11 12 note slave lsb out 9 3 lsb in 2 7 bit 6? msb out 10 a) spi slave timing (cpha = 0) a) spi slave timing (cpha = 1) 9-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 386 specifications motorola cgm operating conditions cgm component information characteristic symbol min typ max comments operating voltage v dd 4.5 v 5.5 v crystal reference frequency f rclk 1 4.9152 mhz 8 module crystal reference frequency f xclk 4.9152 mhz same frequency as f rclk range nom. multiplier (mhz) f nom 4.9152 4.5?.5 v, v dd only vco center-of-range frequency (mhz) f vrs 4.9152 32.0 4.5?.5 v, v dd only vco operating frequency (mhz) f vclk 4.9152 32.0 description symbol min typ max comments crystal load capacitance c l consult crystal manufacturer s data crystal fixed capacitance c1 2 x cl consult crystal manufacturer s data crystal tuning capacitance c2 2 x cl consult crystal manufacturer s data filter capacitor multiply factor c fact 0.0154 f/s v filter capacitor c f c fact x (v dda / f xclk ) see external ?ter capacitor pin (cgmxfc) on page 102 . bypass capacitor c byp 0.1 m f cbyp must provide low ac impedance from f = f xclk /100 to 100 x f vclk , so series resistance must be considered. 10-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications cgm acquisition/lock time information MC68HC08AZ32 motorola specifications 387 cgm acquisition/lock time information description symbol min typ max notes manual mode time to stable t acq (8 x v dda )/(f xclk x k acq) if c f chosen correctly manual stable to lock time t al (4 x v dda )/(f xclk x k trk ) if c f chosen correctly manual acquisition time t lock ? acq +t al tracking mode entry frequency tolerance d trk 0 3.6% acquisition mode entry frequency tolerance d unt 6.3% 7.2% lock entry freq. tolerance d lock 0 0.9% lock exit freq. tolerance d unl 0.9% 1.8% reference cycles per acquisition mode measurement n acq ?2 reference cycles per tracking mode measurement n trk 128 automatic mode time to stable t acq n acq /f xclk (8 x v dda )/(f xclk x k acq) if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4 x v dda )/(f xclk x k trk ) if c f chosen correctly automatic lock time t lock ? acq +t al pll jitter, deviation of average bus frequency over 2 ms 0 (f crys ) x (.025%) x (n/4) n = vco freq. mult. (gbnt) 1. gbnt guaranteed but not tested 2.v dd = 5.0 vdc 0.5v, v ss = 0 vdc, t a = ?0 c to t a (max) , unless otherwise noted. 11-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 388 specifications motorola timer module characteristics memory characteristics characteristic symbol min max unit input capture pulse width t tih, t til 125 ns input clock pulse width t tch, t tcl (1/f op ) + 5 ns characteristic symbol min max unit ram data retention voltage v rdr 0.7 v eeprom programming time per byte t eepgm 10 ms eeprom erasing time per byte t eebyte 10 ms eeprom erasing time per block t eeblock 10 ms eeprom erasing time per bulk t eebulk 10 ms eeprom programming voltage discharge period t eefpv 100 m s eeprom write/erase cycles @ 10 ms write time +125 c 10,000 cycles eeprom data retention after 10,000 write/erase cycles 10 years eeprom enable recovery time t eeoff 600 m s eeprom stop recovery time t eestop 600 m s 12-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications mechanical specifications MC68HC08AZ32 motorola specifications 389 mechanical specifications 64-pin quad flat pack (qfp) figure 3. 64-pin qfp (case #840c) 32 48 49 64 1 16 17 33 detail c -b- -a- -c- -d- -h- m b a c l s v g h e m l !! !! detail a k -h- u q r t w x detail c b b p -a-, -b-, d- detail a j f base metal d n section b-b "! ! " ! ' " ! " "# (( ! " " "" ! " %" " % " &"! " !" ' " " "" " " "# ! (( " " " "# (( ! ! ! $ " " " !" (( ! ! " # " #! % " #! ! ! ! ! # ! " " " "# (( ! ! " # " #! % " #! ! " " &!! " ! " & # " " " " " % #! " " ! ! ! ! ! ! ) ) ) ! ! ) ) ! ! ) 13-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specitcations MC68HC08AZ32 390 specifications motorola 14-specs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola appendix a: future eeprom registers 391 appendix a: future eeprom registers appendix a: future eeprom registers note: the following are proposed register addresses. writing to them in current software will have no effect. eeprom timebase divider control registers to program or erase the eeprom content, the eeprom control hardware requires a constant timebase of 35 m s to drive its internal timer. eeprom timebase divider eediv is a clock-divider which divides the selected reference clock source to generate this constant timebase. the reference clock input of the eediv is driven by either the cgmxclk or the system bus clock. the selection of this reference clock is defined by the eedivclk bit in the configuration register. eeprom timebase divider eediv are defined by two registers (eedivh and eedivl) and must be programmed with a proper value before starting any eeprom erase/program steps. eediv registers must be re-programmed when ever its reference clock is changed. the eediv value can be either pre-programmed in the eedivhnvr and eedivlnvr non-volatile memory registers, (which upon reset will load their contents into the eedivh and eedivl registers,) or programmed directly by software into the eedivh and eedivl registers at system initialization. the function of the divider is to provide a constant clock source with a period of 35 m s (better be within ?2ms) to the internal timer and related eeprom circuits for proper program/erase operations. the recommended frequency range of the reference clock is 250khz to 32mhz. 1-appa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . appendix a: future eeprom registers MC68HC08AZ32 392 appendix a: future eeprom registers motorola eedivh and eedivl registers eedivh and eedivl are used to store the 11-bit eediv value which can be programmed by software at system initialization or during runtime if the eedivsecd bit in the eedivh is not cleared. the eediv value is calculated by the following formula: where the result inside the bracket [ ] is rounded down to the nearest integer value. for example, if the reference frequency is 4.9152mhz, the eediv value in the above formula will be 172. to examine the timebase output of the divider, the reference frequency is divided by the calculated eediv value (172), which equals to 28.577khz in frequency or 34.99 m s in period. programming/erasing the eeprom with an improper eediv value may result in data loss and reduce endurance of the eeprom device. eediv int reference frequency (hz) 35 10 6 0.5 + [] = address: $fe1a bit 7 654321 bit 0 read: eedivsecd eediv10 eediv9 eediv8 write: reset: eedivh-nvr xxxx eedivh-nvr eedivh-nvr eedivh-nvr = unimplemented figure 4. eeprom-2 divider high register (eedivh) address: $fe1b bit 7 654321 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: eedivh-nvr eedivh-nvr eedivh-nvr eedivh-nvr eedivh-nvr eedivh-nvr eedivh-nvr eedivh-nvr = unimplemented figure 5. eeprom-2 divider low register (eedivl) 2-appa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . appendix a: future eeprom registers eediv non-volatile registers MC68HC08AZ32 motorola appendix a: future eeprom registers 393 3-appa eedivsecd ?eeprom divider security disable this bit enables/disables the security feature of the eediv registers. when eediv security feature is enabled, the state of the registers eedivh and eedivl are locked (including this eedivsecd bit). also the eedivhnvr and eedivlnvr non-volatile memory registers are protected from being erased/programmed. 1 = eediv security feature disabled 0 = eediv security feature enabled eediv10?ediv0 ?eeprom timebase prescaler. these prescaler bits store the value of eediv which is used as the divisor to derive a timebase of 35 m s from the selected reference clock source for the eeprom related internal timer and circuits. eediv0?0 are readable at any time. they are writable when eelat is not set and eedivsecd is not cleared. eediv non-volatile registers address: $fe10 bit 7 654321 bit 0 read: eedivsecd eediv10 eediv9 eediv8 write: reset: pv pv pv pv pv pv pv pv = unimplemented figure 6. eeprom-2 divider high non-volatile register (eedivhnvr) address: $fe11 bit 7 654321 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: pv pv pv pv pv pv pv pv = unimplemented figure 7. eeprom-2 divider low non-volatile register (eedivlnvr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . appendix a: future eeprom registers MC68HC08AZ32 394 appendix a: future eeprom registers motorola pv = programmed value or ??in the erased state. the eeprom divider non-volatile registers (eedivhnvr and eedivlnvr) store the reset values of the eediv0?0 and eedivsecd bits which are non-volatile and are not modified by reset. on reset, these two special registers load the eediv0?0 and eedivsecd bits into the corresponding volatile eediv registers (eedivh and eedivl). the eedivhnvr and eedivlnvr can be programmed/erased like normal eeprom bytes if the divider security disable bit (eedivsecd) in the eedivh is not cleared. the new 11-bit eediv value in the non-volatile registers (eedivhnvr and eedivlnvr) together with the eeprom divider security disable bit (eedivsecd) will only be loaded into the eedivh & eedivl registers with a system reset. note: once eedivsecd in the eedivhnvr is programmed to ??and after a system reset, the eediv security feature is permanently enabled because the eedivsecd bit in the eedivh is always loaded with a ?? thereafter. once this security feature is armed, erase and program modes are disabled for eedivhnvr and eedivlnvr. modifications to the eedivh and eedivl registers are also disabled. therefore, great care should be taken before programming a value into the eedivhnvr. 4-appa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola glossary 395 glossary glossary a ?see ?ccumulator (a). accumulator (a) ?an 8-bit general-purpose register in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode ?a mode of pll operation during startup before the pll locks on a frequency. also see "tracking mode." address bus ?the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ?the way that the cpu determines the operand address for an instruction. the m68hc08 cpu has 16 addressing modes. alu ?see ?rithmetic logic unit (alu). arithmetic logic unit (alu) ?the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous ?refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate ?the total number of bits transmitted per unit of time. bcd ?see ?inary-coded decimal (bcd). binary ?relating to the base 2 number system. binary number system ?the base 2 number system, having two digits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (bcd) ?a notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 396 glossary motorola bit ?a binary digit. a bit has a value of either logic 0 or logic 1. branch instruction ?an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module ?a module in the m68hc08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ?a number written into the break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). break interrupt ?a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus ?a set of wires that transfers logic signals. bus clock ?the bus clock is derived from the cgmout output from the cgm. the bus clock frequency, f op , is equal to the frequency of the oscillator output, cgmxclk, divided by four. byte ?a set of eight bits. c ?the carry/borrow bit in the condition code register. the cpu08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). ccr ?see ?ondition code register. central processor unit (cpu) ?the primary functioning unit of any computer system. the cpu controls the execution of instructions. cgm ?see ?lock generator module (cgm). clear ?to change a bit from logic 1 to logic 0; the opposite of set. clock ?a square wave signal used to synchronize events in a computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 motorola glossary 397 clock generator module (cgm) ?a module in the m68hc08 family. the cgm generates a base clock signal from which the system clocks are derived. the cgm may include a crystal oscillator circuit and or phase-locked loop (pll) circuit. comparator ?a device that compares the magnitude of two inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (cop) ?a counter module in the m68hc08 family that resets the mcu if allowed to overflow. condition code register (ccr) ?an 8-bit register in the cpu08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit ?one bit of a register manipulated by software to control the operation of the module. control unit ?one of two major units of the cpu. the control unit contains logic functions that synchronize the machine and direct various operations. the control unit decodes instructions and generates the internal control signals that perform the requested operations. the outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (alu), cpu registers, and bus interface. cop ?see "computer operating properly module (cop)." counter clock ?the input clock to the tim counter. this clock is the output of the tim prescaler. cpu ?see ?entral processor unit (cpu). cpu08 ?the central processor unit of the m68hc08 family. cpu clock ?the cpu clock is derived from the cgmout output from the cgm. the cpu clock frequency is equal to the frequency of the oscillator output, cgmxclk, divided by four. cpu cycles ?a cpu cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. the length of time required to execute an instruction is measured in cpu clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 398 glossary motorola cpu registers ?memory locations that are wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the information in these registers. the cpu registers in an m68hc08 are: a (8-bit accumulator) h:x (16-bit index register) sp (16-bit stack pointer) pc (16-bit program counter) ccr (condition code register containing the v, h, i, n, z, and c bits) csic ?customer-specified integrated circuit cycle time ?the period of the operating frequency: t cyc = 1/f op . decimal number system ?base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ?a m68hc08 family module that can perform data transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma transfers are faster and more code-efficient than cpu interrupts. dma ?see "direct memory access module (dma)." dma service request ?a signal from a peripheral to the dma module that enables the dma module to transfer data. duty cycle ?a ratio of the amount of time the signal is on versus the time it is off. duty cycle is usually represented by a percentage. eeprom ?electrically erasable, programmable, read-only memory. a nonvolatile type of memory that can be electrically reprogrammed. eprom ?erasable, programmable, read-only memory. a nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ?an event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 motorola glossary 399 external interrupt module (irq) ?a module in the m68hc08 family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch ?to copy data from a memory location into the accumulator. firmware ?instructions and data programmed into nonvolatile memory. free-running counter ?a device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission ?communication on a channel in which data can be sent and received simultaneously. h ?the upper byte of the 16-bit index register (h:x) in the cpu08. h ?the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instruction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ?base 16 numbering system that uses the digits 0 through 9 and the letters a through f. high byte ?the most significant eight bits of a word. illegal address ?an address not within the memory map illegal opcode ?a nonexistent opcode. i ?the interrupt mask bit in the condition code register of the cpu08. when i is set, all interrupts are disabled. index register (h:x) ?a 16-bit register in the cpu08. the upper byte of h:x is called h. the lower byte is called x. in the indexed addressing modes, the cpu uses the contents of h:x to determine the effective address of the operand. h:x can also serve as a temporary data storage location. input/output (i/o) ?input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 400 glossary motorola instructions ?operations that a cpu can perform. instructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode and its associated operand(s) and instruction. interrupt ?a temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request ?a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o ?see ?nput/output (i/0). irq ?see "external interrupt module (irq)." jitter ?short-term signal instability. latch ?a circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ?the time lag between instruction completion and data movement. least significant bit (lsb) ?the rightmost digit of a binary number. logic 1 ?a voltage level approximately equal to the input power voltage (v dd ). logic 0 ?a voltage level approximately equal to the ground voltage (v ss ). low byte ?the least significant eight bits of a word. low voltage inhibit module (lvi) ?a module in the m68hc08 family that monitors power supply voltage. lvi ?see "low voltage inhibit module (lvi)." m68hc08 ?a motorola family of 8-bit mcus. mark/space ?the logic 1/logic 0 convention used in formatting data in serial communication. mask ?1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integrated circuit fabrication to transfer an image onto silicon. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 motorola glossary 401 mask option ?a optional microcontroller feature that the customer chooses to enable or disable. mask option register (mor) ?an eprom location containing bits that enable or disable certain mcu features. mcu ?microcontroller unit. see ?icrocontroller. memory location ?each m68hc08 memory location holds one byte of data and has a unique address. to store information in a memory location, the cpu places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the selected memory location places its data onto the data bus. memory map ?a pictorial representation of all memory locations in a computer system. microcontroller ?microcontroller unit (mcu). a complete computer system, including a cpu, memory, a clock oscillator, and input/output (i/o) on a single integrated circuit. modulo counter ?a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ?a section of rom that can execute commands from a host computer for testing purposes. mor ?see "mask option register (mor)." most significant bit (msb) ?the leftmost digit of a binary number. multiplexer ?a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ?the negative bit in the condition code register of the cpu08. the cpu sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble ?a set of four bits (half of a byte). object code ?the output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 402 glossary motorola opcode ?a binary code that instructs the cpu to perform an operation. open-drain ?an output that has no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ?data on which an operation is performed. usually a statement consists of an operator and an operand. for example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator ?a circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ?one-time programmable read-only memory. a nonvolatile type of memory that cannot be reprogrammed. overflow ?a quantity that is too large to be contained in one byte or one word. page zero ?the first 256 bytes of memory (addresses $0000?00ff). parity ?an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even number of logic 1s. in the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver counts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. pc ?see ?rogram counter (pc). peripheral ?a circuit not under direct cpu control. phase-locked loop (pll) ?a oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. pll ?see "phase-locked loop (pll)." pointer ?pointer register. an index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity ?the two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, v dd and v ss . polling ?periodically reading a status bit to monitor the condition of a peripheral device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 motorola glossary 403 port ?a set of wires for communicating with off-chip devices. prescaler ?a circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program ?a set of computer instructions that cause a computer to perform a desired operation or operations. program counter (pc) ?a 16-bit register in the cpu08. the pc register holds the address of the next instruction or operand that the cpu will use. pull ?an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup ?a transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width ?the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ?controlled variation (modulation) of the pulse width of a signal with a constant frequency. push ?an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period ?the time required for one complete cycle of a pwm waveform. ram ?random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit ?a circuit consisting of capacitors and resistors having a defined time constant. read ?to copy the contents of a memory location to the accumulator. register ?a circuit that stores a group of bits. reserved memory location ?a memory location that is used only in special factory test modes. writing to a reserved location has no effect. reading a reserved location returns an unpredictable value. reset ?to force a device to a known condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 404 glossary motorola rom ?read-only memory. a type of memory that can be read but cannot be changed (written). the contents of rom must be specified before manufacturing the mcu. sci ?see "serial communication interface module (sci)." serial ?pertaining to sequential transmission over a single line. serial communications interface module (sci) ?a module in the m68hc08 family that supports asynchronous communication. serial peripheral interface module (spi) ?a module in the m68hc08 family that supports synchronous communication. set ?to change a bit from logic 0 to logic 1; opposite of clear. shift register ?a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed ?a binary number notation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. software ?instructions and data that control the operation of a microcontroller. software interrupt (swi) ?an instruction that causes an interrupt and its associated vector fetch. spi ?see "serial peripheral interface module (spi)." stack ?a portion of ram reserved for storage of cpu register contents and subroutine return addresses. stack pointer (sp) ?a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit ?a bit that signals the beginning of an asynchronous serial transmission. status bit ?a register bit that indicates the condition of a device. stop bit ?a bit that signals the end of an asynchronous serial transmission. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 motorola glossary 405 subroutine ?a sequence of instructions to be used more than once in the course of a program. the last instruction in a subroutine is a return from subroutine (rts) instruction. at each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, the cpu returns to the main program where it left off. synchronous ?refers to logic circuits and operations that are synchronized by a common reference signal. tim ?see "timer interface module (tim)." timer interface module (tim) ?a module used to relate events in a system to a point in time. timer ?a module used to relate events in a system to a point in time. toggle ?to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ?mode of low-jitter pll operation during which the pll is locked on a frequency. also see "acquisition mode." two? complement ?a means of performing binary subtraction using addition techniques. the most significant bit of a two? complement number indicates the sign of the number (1 indicates negative). the two? complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered ?utilizes only one register for data; new data overwrites current data. unimplemented memory location ?a memory location that is not used. writing to an unimplemented location has no effect. reading an unimplemented location returns an unpredictable value. executing an opcode at an unimplemented location causes an illegal address reset. v ?he overflow bit in the condition code register of the cpu08. the cpu08 sets the v bit when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ?a value that changes during the course of program execution. vco ?see "voltage-controlled oscillator." f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC08AZ32 406 glossary motorola vector ?a memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) ?a circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform ?a graphical representation in which the amplitude of a wave is plotted against time. wired-or ?connection of circuit outputs so that if any output is high, the connection point is high. word ?a set of two bytes (16 bits). write ?the transfer of a byte of data from the cpu to a memory location. x ?the lower byte of the index register (h:x) in the cpu08. z ?the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola index 407 index index a accumulator (a) . . . . . . . . . . . . . . . . . . . . . .53 ack1 bit (irq interrupt request acknowledge bit) . . . . . . . . . . . . . . . . . .156 , 159 161 ackk keyboard acknowledge bit . . . . . . . . . .304 acq pbwc . . . . . . . . . . . . . . . . . . . . . . . . .108 adc analog ground pin (avss/vrefl) . . . .293 analog power pin (vddaref) . . . . . . .293 continuous conversion . . . . . . . . . . . . .291 conversion time . . . . . . . . . . . . . . . . . .290 interrupts . . . . . . . . . . . . . . . . . . . . . . .291 port i/o pins . . . . . . . . . . . . . . . . . . . . .290 voltage conversion . . . . . . . . . . . . . . . .290 voltage in (advin) . . . . . . . . . . . . . . . .293 voltage reference pin (vrefh) . . . . . .293 adc characteristics . . . . . . . . . . . . . . . . . .382 adc clock register (adclkr) . . . . . . . . . .297 adc data register (adr) . . . . . . . . . . . . . .297 adc status and control register (adscr) 294 adco - adc continuous conversion . . . . . . . . . . . . .295 adiclk adc input clock select . . . . . . . . . . . . .298 aien - adc interrupt enable . . . . . . . . . . . . . . . . . .295 arithmetic/logic unit (alu) . . . . . . . . . . . . . .57 auto pbwc . . . . . . . . . . . . . . . . . . . . . . . . .107 b baud rate sci module . . . . . . . . . . . . . . . . . . . . .195 bcfe sbfcr . . . . . . . . . . . . . . . . . . . . . . . . . 90 bcfe bit (break clear flag enable bit) 90 , 160 , 180 bcs pctl . . . . . . . . . . . . . . . . . . . . . . . . . . 106 bih instruction . . . . . . . . . . . . . . . . . . . . . . 159 bil instruction . . . . . . . . . . . . . . . . . . . . . . 159 bkf bit (sci break flag bit) . . . . . . . . . . . . 193 bkpt signal . . . . . . . . . . . . . . . . . . . . . . . 124 block diagram cgm . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 break character . . . . . . . . . . . . . . . . . . . . . 170 break interrupt . . . . . . . . . . . . . . . . . . . . 80 , 83 causes . . . . . . . . . . . . . . . . . . . . . . . . . 124 during wait mode . . . . . . . . . . . . . . . . . . 85 effects on cop . . . . . . . . . . . . . . 126 , 148 effects on cpu . . . . . . . . . . . . . . . 58 , 126 effects on pit . . . . . . . . . . . . . . . . . . . 282 effects on spi . . . . . . . . . . . . . . . . . . . 219 effects on tim . . . . . . . . . . . . . . . 126 , 268 effects on tima . . . . . . . . . . . . . . . . . . 244 flag protection during . . . . . . . . . . . . . . . 84 break module break address registers (brkh/l) . . . 124 , 126 127 break status and control register (brk- scr) . . . . . . . . . . . . . . . . . 124 , 127 break signal . . . . . . . . . . . . . . . . . . . . . . . . 136 brka bit (break active bit) . . . . . . . . 124 , 127 brke bit (break enable bit) . . . . . . . . . . . 127 bus frequency . . . . . . . . . . . . . . . . . . . . . . . 52 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 73 c c bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 408 index motorola ccr c bit (carry/borrow flag) . . . . . . . . . . . . .57 h bit (half-carry flag) . . . . . . . . . . . . . . .56 i bit (interrupt mask) . . . . . . . . . . . . . . . .56 n bit (negative flag) . . . . . . . . . . . . . . . .57 v bit (overflow flag) . . . . . . . . . . . . . . . .56 z bit (zero flag) . . . . . . . . . . . . . . . . . . . .57 cgm base clock output (cgmout) . . . . . . .103 clock signals . . . . . . . . . . . . . . . . . . . . . .72 cpu interrupt (cgmint) . . . . . . . . . . .103 crystal oscillator circuit . . . . . . . . . . . . . .95 external connections . . . . . . . . . . . . . .101 interrupts . . . . . . . . . . . . . . . . . . . . . . .111 phase-locked loop (pll) circuit . . . . . . .95 pll bandwidth control register (pbwc) . . . 97 , 107 pll control register (pctl) . . . . . . . . .105 pll programming register (ppg) . . . .109 cgm acquisition/lock time information . . .387 cgm component information . . . . . . . . . .386 cgm operating conditions . . . . . . . . . . . . .386 cgmrclk signal . . . . . . . . . . . . . . . . . . . .95 cgmrdv signal . . . . . . . . . . . . . . . . . . . . .96 cgmvdv signal . . . . . . . . . . . . . . . . . . . . .96 cgmxclk signal . . . . . . . . . . . . . . .145 146 duty cycle . . . . . . . . . . . . . . . . . . . . . . .103 cgmxfc pin . . . . . . . . . . . . . . . . . . . . . . . .15 cgnd/ev ss pin . . . . . . . . . . . . . . . . . . . . .222 chxf bits (tim channel interrupt flag bits) . . . . 251 , 275 chxie bits (tim channel interrupt enable bits) 251 , 275 chxmax bits (tim maximum duty cycle bits) . 254 , 277 cli instruction . . . . . . . . . . . . . . . . . . . . . . .56 clock generator module (cgm) . . . . . .92 118 block diagram . . . . . . . . . . . . . . . . . . . . .94 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . .73 clock start-up from lvi reset . . . . . . . . . . . .73 coco/idmas conversions complete/interrupt dma se- lect . . . . . . . . . . . . . . . . . . . . . . 294 condition code register (ccr) . . . . . . . 55 , 157 control timing . . . . . . . . . . . . . . . . . . . . . . . 381 cop bit (computer operating properly reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . 145 cop control register (copctl) . . . . 146 147 cop counter . . . . . . . . . . . . . . . 143 , 145 148 cop timeout period . . . . . . . . . . . . . 145 , 148 copd mora . . . . . . . . . . . . . . . . . . . . . . . . . 121 coprs mora . . . . . . . . . . . . . . . . . . . . . . . . . 121 cpha bit (spi clock phase bit) . 206 , 221 , 224 cpol bit (spi clock polarity bit) . . . . . . . . 224 cpu interrupt software . . . . . . . . . . . . . . . . . . . . . 58 , 134 cpu interrupt requests sci . . . . . . . . . . . . . . . . . . . . . . . . 178 179 cpu interrupts hardware . . . . . . . . . . . . . . . . . . . . . 80 , 82 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 software . . . . . . . . . . . . . . . . . . . 80 , 82 83 spi . . . . . . . . . . . . . . . . . . . . 215 , 218 , 226 tim . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 tim input capture . . . . . . . . . . . . . . . . . 236 tim output compare . . . . . . . . . . . . . . 236 tima overflow . . . . . . . . . . . . . . . . . . . 243 cpu registers h register . . . . . . . . . . . . . . . . . . . . . . . . 35 stack pointer . . . . . . . . . . . . . . . . . . . . . 35 crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . 101 crystal . . . . . . . . . . . . . . . . . . . . . . . . 145 146 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal output frequency signal (cgmxclk) . 103 d dc electrical characteristics . . . . . . . . . . . 380 dma service requests spi . . . . . . . . . . . . . . . . . . . . . . . . 215 , 226 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 motorola index 409 e eeacr eeprom array configuration register . .48 eecr eeprom control register . . . . . . . . . . . .46 eenvr eeprom non-volatile register . . . . . . . .48 eeprom . . . . . . . . . . . . . . . . . . . . . . . .40 49 block protection . . . . . . . . . . . . . . . . . . .44 configuration . . . . . . . . . . . . . . . . . . . . .44 eeacr . . . . . . . . . . . . . . . . . . . . . . . . . .48 eecr . . . . . . . . . . . . . . . . . . . . . . . . . . .46 eenvr . . . . . . . . . . . . . . . . . . . . . . . . . .48 erasing . . . . . . . . . . . . . . . . . . . . . . . . . .42 programming . . . . . . . . . . . . . . . . . . . . .41 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 eeprom control register (eecr1) . .392 393 eesec morb . . . . . . . . . . . . . . . . . . . . . . . . .122 electrostatic damage . . . . . . . . . . . . . . . . .308 elsxa/b bits (tim edge/level select bits) 252 , 276 ensci bit (enable sci bit) . . . . . . . . .169 , 182 eprom/otprom security . . . . . . . . . . . .120 external crystal . . . . . . . . . . . . . . . . . . . . . .87 external filter capacitor . . . . . . . . . . .102 , 115 external filter capacitor pin (cgmxfc) . . .102 external pin reset . . . . . . . . . . . . . . . . . . . . .74 f f bus (bus frequency) . . . . . . . . . . . . . . . . . . .99 fe bit (sci framing error bit) . . . . . . . . . . .178 fe bit (sci receiver framing error bit) . . . .192 feie bit (sci framing error interrupt enable bit) 178 feie bit (sci receiver framing error interrupt enable bit) . . . . . . . . . . . . . . . . . . . .189 flag protection in break mode . . . . . . . . . . .84 f nom (nominal center-of-range frequency) . .96 f rclk (pll reference clock frequency) . . . . . .99 f rclk (pll reference clock frequency) . . . . .96 f rdv (pll final reference frequency) . . . . . .96 functional operating range . . . . . . . . . . . . .379 f vclk (vco output frequency) . . . . . . . . . . . 96 f vrs (vco programmed center-of-range fre- quency) . . . . . . . . . . . . . . . 96 , 99 , 110 h h bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 i i bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 i bit (interrupt mask) . . . . . . . . . . . . . 157 , 161 i/o port register summary . . . . . . . . . . . . . 308 i/o registers locations . . . . . . . . . . . . . . . . . . . . . . . . 24 iab (internal address bus) . . . . . . . . . . . . 124 ibus . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 , 79 idle bit (sci receiver idle bit) . . . . . . 178 , 190 idle character . . . . . . . . . . . . . . . . . . . . . . 171 ilad srsr . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ilie bit (sci idle line interrupt enable bit) 178 , 186 ilop srsr . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ilop bit (illegal opcode reset bit) . . . . . . . . 90 ilty bit (sci idle line type bit) . . . . . . . . . 183 imask1 bit (irq interrupt mask bit) . 157 , 161 imaskk keyboard interrupt mask bit . . . . . . . . . 304 index register (h:x) . . . . . . . . . . . . . . . . 54 , 82 input capture . . . . . . . . . . . . . . . 236 , 261 , 278 interrupt external interrupt pin (irq ) . . . . . . . . . . 15 interrupt status and control register (iscr) . . 156 interrupts adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 cgm . . . . . . . . . . . . . . . . . . . . . . . . . . 111 mscan08 . . . . . . . . . . . . . . . . . . . . . . 341 irq latch . . . . . . . . . . . . . . . . . . . . . . . . . . 156 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 irq status and control register (iscr) . . . 160 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 410 index motorola irq /v pp pin . . . . . . . . . . . . . . . . .15 , 155 , 159 triggering sensitivity . . . . . . . . . . . . . . .156 irq1 /v pp pin . . . . . . . . . . . . . . . . . . . . . . .147 irst signal . . . . . . . . . . . . . . . . . . . . . . . . .74 k kb i/o register summary . . . . . . . . . . . . . .301 kbie4-kbie0 keyboard interrupt enable bits . . . . . . .304 keyboard interrupt control register (kbicr) . . . 303 keyboard interrupt enable register (kbier) . . 304 keyf keyboard flag bit . . . . . . . . . . . . . . . . .303 l l (vco linear range multiplier) . . . . . . . . . .99 literature distribution centers . . . . . . . . . . .417 lock pbwc . . . . . . . . . . . . . . . . . . . . . . . . .107 loops bit (sci loop mode select bit) . . . .182 lvi srsr . . . . . . . . . . . . . . . . . . . . . . . . . . .90 lvi module . . . . . . . . . . . . . . . . . . . . . . . .153 lvi status register (lvisr) . . . . . . . .150 , 152 lvi trip voltage . . . . . . . . . . . . . . . . . . . . .149 lviout bit (lvi output bit) . . . . . . . .150 , 152 lvipwr mora . . . . . . . . . . . . . . . . . . . . . . . . .120 lvipwr bit (lvi power enable bit) . . . . . .153 lvirst mora . . . . . . . . . . . . . . . . . . . . . . . . .120 lvirst bit ( lvi reset bit) . . . . . . . . . . . . .150 lvirst bit (lvi reset enable bit) . . . . . . . .153 m m bit (sci mode (character length) bit) . . 168 , 170 , 182 mask option register a (mora) . . . . . . . . . . . . . . . .120 register b (morb) . . . . . . . . . . . . . . . .122 mask option register (mor) . . . . . . . 148 , 151 maximum ratings . . . . . . . . . . . . . . . . . . . . 378 memory characterisitcs . . . . . . . . . . . . . . . 388 memory map mscan08 . . . . . . . . . . . . . . . . . . . . . . 354 mode1 bit (irq edge/level select bit) . . 156 , 159 , 161 modek keyboard triggering sensitivity bit . . . . 304 modf bit (spi mode fault bit) . . . . . . . . . . 227 monitor commands iread . . . . . . . . . . . . . . . . . . . . . . . . . 138 iwrite . . . . . . . . . . . . . . . . . . . . . . . . 138 read . . . . . . . . . . . . . . . . . . . . . . . . . . 137 readsp . . . . . . . . . . . . . . . . . . . . . . . 139 run . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 write . . . . . . . . . . . . . . . . . . . . . . . . . 137 monitor mode . . . . . . . . . . . . . . . . . . 126 , 147 alternate vector addresses . . . . . . . . . 134 baud rate . . . . . . . . . . . . . . . . . . . . . . . 132 commands . . . . . . . . . . . . . . . . . . . . . . 132 echoing . . . . . . . . . . . . . . . . . . . . . . . . 136 eprom/otprom programming . . . . 132 monitor rom size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 mora cop disable bit (copd) . . . . . . . . . . . 121 cop rate select (coprs) . . . . . . . . . . 121 lvi power enable bit (lvipwr) . . . . . . 120 lvi reset enable bit (lvirst) . . . . . . . 120 rom security bit (sec) . . . . . . . . . . . . 120 short stop recovery bit (ssrec) . . . . . 121 stop enable bit (stop) . . . . . . . . . . . 121 morb eeprom security enable bit (eesec) 122 mscan08 bus timing register 0 (cbtr0) . . . . . . . 364 bus timing register 1 (cbtr1) . . . . . . . 365 clock system . . . . . . . . . . . . . . . . . . . . 351 control register structure . . . . . . . . . . . 360 cpu wait mode . . . . . . . . . . . . . . . . . 350 data length register (dlr) . . . . . . . . . . 358 data segment registers (dsrn) . . . . . 358 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 motorola index 411 external pins . . . . . . . . . . . . . . . . . . . . .334 identifier acceptance control register (ci- dac) . . . . . . . . . . . . . . . . . . . . .372 identifier acceptance filter . . . . . . . . . .340 identifier acceptance registers (cidar0-3) . . . . . . . . . . . . . . . .374 identifier mask registers (cidmr0-3) .375 identifier registers (idrn) . . . . . . . . . . .356 internal sleep mode . . . . . . . . . . . . . . .348 interrupt acknowledge . . . . . . . . . . . . .344 interrupt vectors . . . . . . . . . . . . . . . . . .344 interrupts . . . . . . . . . . . . . . . . . . . . . . .341 memory map . . . . . . . . . . . . . . . . . . . .354 message buffer organization . . . . . . . .338 message buffer outline . . . . . . . . . . . . .355 message storage . . . . . . . . . . . . . . . . .335 module control register (cmcr0) . . . .361 module control register (cmcr1) . . . .363 programmable wake-up function . . . . .350 receive error counter (crxerr) . . . .373 receive structures . . . . . . . . . . . . . . . . .336 receiver flag register (crflg) . . . . . . .366 receiver interrupt enable register (crier) . 369 transmit buffer priority registers (tbpr) . . 359 transmit error counter (ctxerr) . . .374 transmit structures . . . . . . . . . . . . . . . .339 transmitter control register (ctcr) .371 transmitter flag register (ctflg) . . .370 msxa/b bits (tim mode select bits) 252 , 254 , 275 , 278 n n bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 neie bit (sci noise error interrupt enable bit) . 178 , 191 neie bit (sci receiver noise error interrupt en- able bit) . . . . . . . . . . . . . . . . . . . . . .188 nf bit (sci noise flag bit) . . . . . . . . .178 , 191 o or bit (sci receiver overrun bit) . . . . 178 , 191 ordering information literature distribution centers . . . . . . . . 417 mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 web server . . . . . . . . . . . . . . . . . . . . . 418 web site . . . . . . . . . . . . . . . . . . . . . . . . 418 orie bit (sci overrun interrupt enable bit) . . . 178 orie bit (sci receiver overrun interrupt en- able bit) . . . . . . . . . . . . . . . . . . . . . 188 osc1 pin . . . . . . . . . . . . . . . . . . . . . . 15 , 102 osc2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 15 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 146 oscillator enable signal (simoscen) . . . . 103 oscillator pins osc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output compare . . . . . . . . . . . . . 236 , 261 , 278 buffered . . . . . . . . . . . . . . . . . . . . 237 , 262 unbuffered . . . . . . . . . . . . . . . . . . 236 , 261 ovrf bit (spi overflow bit) . . . . . . . . . . . . 227 p page zero . . . . . . . . . . . . . . . . . . . . . . . . . . 55 parity sci module . . . . . . . . . . . . . . . . . 178 , 181 pbwc acquisition mode bit (acq ) . . . . . . . . . 108 automatic bandwidth control bit (auto) . . 107 crystal loss detect bit (xld) . . . . . . . . . 108 lock indicator bit (lock) . . . . . . . . . . . 107 pctl base clock select bit (bcs) . . . . . . . . . 106 pll interrupt enable bit (pllie) . . . . . 105 pll interrupt flag bit (pllf) pllf pctl 105 pll on bit (pllon) . . . . . . . . . . . . . . . 106 pe bit (sci parity error bit) . . . . . . . . . . . . 178 pe bit (sci receiver parity error bit) . . . . . 192 peie bit (sci parity error interrupt enable bit) 178 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 412 index motorola peie bit (sci receiver parity error interrupt en- able bit) . . . . . . . . . . . . . . . . . . . . . .189 pen bit (sci parity enable bit) . . . . . . . . .183 phase-locked loop (pll) . . . . . . . . . . .95 101 acquisition mode . . . . . . . . . . .95 , 97 , 114 acquisition time . . . . . . . . . . . . . . . . . .114 automatic bandwidth mode . . . . . . . . . .97 lock detector . . . . . . . . . . . . . . . . . . . . . .96 loop filter . . . . . . . . . . . . . . . . . . . . . . . .96 manual bandwidth mode . . . . . . . . . . .107 phase detector . . . . . . . . . . . . . . . . . . . .96 programming . . . . . . . . . . . . . . . . . . . . .99 tracking mode . . . . . . . . . . . . . . . . .95 , 97 voltage-controlled oscillator (vco) . . . .97 pie bit (pit overflow interrupt enable bit) .284 pin srsr . . . . . . . . . . . . . . . . . . . . . . . . . . .90 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . .74 pin bit (external reset bit) . . . . . . . . . . . . . .90 pit counter . . . . . . . . . . . . . . . . . . . .280 , 282 pll analog power pin (v dda ) . . . . . . . . . . .103 pllie pctl . . . . . . . . . . . . . . . . . . . . . . . . . .105 pllon pctl . . . . . . . . . . . . . . . . . . . . . . . . . .106 pof bit (pit overflow flag bit) . . . . . . . . . .284 por srsr . . . . . . . . . . . . . . . . . . . . . . . . . . .89 porrst signal . . . . . . . . . . . . . . . . . . . . . .79 port a . . . . . . . . . . . . . . . . . . . . . .16 , 309 310 data direction register a (ddra) . . . . .309 i/o circuit . . . . . . . . . . . . . . . . . . . . . . .310 pin functions . . . . . . . . . . . . . . . . . . . . .310 port a data register (pta) . . . . . . . . . .309 port b . . . . . . . . . . . . . . . . . . . . . .16 , 311 313 data direction register b (ddrb) . . . . .312 i/o circuit . . . . . . . . . . . . . . . . . . . . . . .312 pin functions . . . . . . . . . . . . . . . . . . . . .313 port b data register (ptb) . . . . . . . . . .311 port c . . . . . . . . . . . . . . . . . . . . . .16 , 314 316 data direction register c (ddrc) . . . . .315 i/o circuit . . . . . . . . . . . . . . . . . . . . . . .316 pin functions . . . . . . . . . . . . . . . . . . . . 316 port c data register (ptc) . . . . . . . . . . 314 port d . . . . . . . . . . . . . . . . . . . . . 16 , 317 319 data direction register d (ddrd) . . . . . 318 i/o circuit . . . . . . . . . . . . . . . . . . . . . . . 319 pin functions . . . . . . . . . . . . . . . . . . . . 319 port d data register (ptd) . . . . . . . . . . 317 port e . . . . . . . . . . . . . . . . . . . . . 16 , 320 322 data direction register e (ddre) . . . . . 322 i/o circuit . . . . . . . . . . . . . . . . . . . . . . . 323 pin functions . . . . . . . . . . . . . . . . . . . . 323 port e data register (pte) . . . . . . . . . . 320 port f . . . . . . . . . . . . . . . . . . . . . . 16 , 324 326 data direction register f (ddrf) . . . . . 325 i/o circuit . . . . . . . . . . . . . . . . . . . . . . . 326 pin functions . . . . . . . . . . . . . . . . . . . . 326 port f data register (ptf) . . . . . . . . . . 324 port g . . . . . . . . . . . . . . . . . . . . . 17 , 327 , 329 data direction register g (ddrg) . . . . 327 i/o circuit . . . . . . . . . . . . . . . . . . . . . . . 328 port g data register (ptg) . . . . . . . . . . 327 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data direction register h (ddrh) . . . . . 329 i/o circuit . . . . . . . . . . . . . . . . . . . . . . . 330 port h data register (pth) . . . . . . . . . . 329 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . 14 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ppg multiplier select bits(mul[7 4]) 109 vco range select bits (vrs[7:4]) . . . . 110 program counter (pc) . . . . . . . . . 55 , 126 , 159 programmable interrupt timer status and control register (psc) . . . . 283 programmable interrupt timer (pit) counter modulo registers (pmodh/l) . 286 counter registers (pcnth:pcntl) . . . 285 protocol violation protection . . . . . . . . . . . 346 prst bit (pit reset bit) . . . . . . . . . . . . . . . 284 ps[2:0] bits (tim prescaler select bits) . . 233 , 248 , 272 pshh instruction . . . . . . . . . . . . . . . . . . . . . 56 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 motorola index 413 pstop bit (pit stop bit) . . . . . . . . . . . . . .284 pty bit (sci parity bit) . . . . . . . . . . . . . . . .183 pulh instruction . . . . . . . . . . . . . . . . . . . . .56 pulse-width modulation (pwm) . . . . . . . . .262 duty cycle . . .239 , 242 , 254 , 263 , 266 , 277 initialization . . . . . . . . . . . . . . . . .241 , 265 r r8 bit (sci received bit 8) . . . . . . . . . . . . .188 ram . . . . . . . . . . . . . . . . . . . . . . . . . . .35 36 size . . . . . . . . . . . . . . . . . . . . . . . . . .10 , 23 stack ram . . . . . . . . . . . . . . . . . . . . . . .55 re bit (sci receiver enable bit) . . . . . . . . .186 reset cop . . . . . . . . . . . . . . . . . . . .77 , 143 , 148 external . . . . . . . . . . . . . . . . . . . . . . . . .75 external reset pin (rst ) . . . . . . . . . . . . .15 illegal address . . . . . . . . . . . . . . . . .78 , 90 illegal opcode . . . . . . . . . . . . . . . . . .78 , 90 internal . . . . . . . . . . . . . . . . . . . . . . . . .146 low-voltage inhibit (lvi) . . . . . . . . . . . . .78 power-on . . . . . . . . . . . . . . . . . . . .76 , 146 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 security . . . . . . . . . . . . . . . . . . . . . . . . . .37 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 rpf bit (sci reception in progress flag bit) . . . 193 rst pin . . . . . . . . . . . . . . . . . . . . . . . . . . .145 during por timeout . . . . . . . . . . . . . . . .73 rti instruction . . . . . . . . . . . . . . . .56 , 58 , 124 rwu bit (sci receiver wake-up bit) . . . . .187 s sbfcr break clear flag enable bit (bcfe) . . . . .90 sbk bit (sci send break bit) . . . . . . .170 , 187 sbsr sim break stop/wait statur bit (sbsw) . 88 sbsw sbsr . . . . . . . . . . . . . . . . . . . . . . . . . . .88 scp1?cp0 bits (sci baud rate prescaler bits) . . . . . . . . . . . . . . . . . . . . . . . . .194 scrf bit (sci receiver full bit) . . . . . . . . . 190 scrie bit (sci receiver interrupt enable bit) . 178 scte bit (sci transmitter empty bit) 169 , 171 , 182 , 185 , 190 sctie bit (sci transmitter interrupt enable bit) 169 , 171 , 185 serial communications interface module (sci) baud rate . . . . . . . . . . . . . . . . . . . . . . . 164 baud rate register (scbr) . . . . . . . . . . 194 character format . . . . . . . . . . . . . . . . . 184 control register 1 (scc1) . . . 168 170 , 181 control register 2 (scc2) . . . 169 170 , 184 control register 3 (scc3) . . . . . . . 168 , 187 data register (scdr) . . . . . . . . . . 169 , 194 error conditions . . . . . . . . . . . . . . . . . . 178 framing error . . . . . . . . . . . . . . . . 177 , 192 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . 180 noise error . . . . . . . . . . . . . . . . . . . . . . 191 overrun error . . . . . . . . . . . . . . . . . . . . 188 parity error . . . . . . . . . . . . . . . . . . . . . . 178 status register 1 (scs1) . . . . . . . 169 , 189 status register 2 (scs2) . . . . . . . . . . . 193 serial peripheral interface module (spi) baud rate . . . . . . . . . . . . . . . . . . . . . . . 226 control register (spcr) . . . . . . . . . . . . 223 data register (spdr) . . . . . . . . . . . . . . 229 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . 220 in stop mode . . . . . . . . . . . . . . . . . . . . 218 mode fault error . . . . . . . . . . . . . . . . . . 227 overflow error . . . . . . . . . . . . . . . . . . . . 227 slave select pin . . . . . . . . . . . . . . . . . . 226 status and control register (spscr) . . 226 sim counter power-on reset . . . . . . . . . . . . . . . . . . . . 79 reset states . . . . . . . . . . . . . . . . . . . . . . 79 stop mode recovery . . . . . . . . . . . . . . . . 79 simoscen signal . . . . . . . . . . . . . . . . . . . 95 spe bit (spi enable bit) . . . . . . . . . . . . . . 225 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . 383 spmstr bit (spi master mode bit) . 220 , 224 spr1[1:0] bits (spi baud rate select bits) . 228 sprf bit (spi receiver full bit) . . . . . . . . . 226 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 414 index motorola sprie bit (spi receiver interrupt enable bit) . . 223 spte bit (spi transmitter empty bit) . . . . .227 sptie bit (spi transmitter interrupt enable bit) 225 spwom bit (spi wired-or mode bit) 220 , 224 srsr computer operating properly reset bit (cop) . . . . . . . . . . . . . . . . . . . . .90 external reset bit (pin) . . . . . . . . . . . . . .90 illegal address reset bit (ilad) . . . . . . . .90 illegal opcode reset bit (ilop) . . . . . . . .90 low-voltage inhibit reset bit (lvi) . . . . . .90 power-on reset bit (por) . . . . . . . . . . . .89 ssrec mora . . . . . . . . . . . . . . . . . . . . . . . . .121 stack pointer . . . . . . . . . . . . . . . . . . . . . . . .35 stack pointer (sp) . . . . . . . . . . . . . . . . . . . .54 stack ram . . . . . . . . . . . . . . . . . . . . . . .35 , 55 start bit . . . . . . . . . . . . . . . . . . . . . . . .136 , 169 sci data . . . . . . . . . . . . . . . . . . . . . . . .183 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 sci data . . . . . . . . . . . . . . . . . . . .178 , 182 stop bit (stop enable bit) . . . . . . . . . . .148 stop instruction 87 , 112 , 129 , 146 , 148 , 153 , 179 , 218 , 281 stop mode . . . . . . . . . . . . . . . . . . . . . . . .292 entry timing . . . . . . . . . . . . . . . . . . . . . .87 recovery from interrupt break . . . . . . . . .87 stop mode . . . . . . . . .129 , 145 , 153 , 193 , 281 recovery time . . . . . . . . . . . . . . . . . . . . .73 swi instruction . . . . . . . . . . .58 , 82 , 126 , 134 system inegration module (sim) stop mode . . . . . . . . . . . . . . . . . . . . . .86 system integration module (sim) . . . . . .70 90 break flag control register (sbfcr) . . . .90 break status register (sbsr) . . . . . . . . .88 exception control . . . . . . . . . . . . . . . . . .80 reset status register (srsr) . . . . .89 , 145 sim counter . . . . . . . . . . . . . .79 , 145 146 wait mode . . . . . . . . . . . . . . . . . . . . . .85 t t8 bit (sci transmitted bit 8) . . . . . . . . . . . 188 t8 bit (transmitted sci bit 8) . . . . . . . . . . . 168 tcie bit (sci transmission complete interrupt enable bit) . . . . . . . . . . . . . . . . . . . 185 te bit (sci transmitter enable bit) . . . . . . . 186 te bit (transmitter enable bit) . . . . . . . . . . 169 thermal characteristics . . . . . . . . . . . . . . . 379 tima counter . . . . . . . . . . . . . . . . . . . . . . 244 timer interface module (tim) . . . . . . . . . ?? 278 channel registers (tch0h/l?ch3h/l) . . 278 timer interface module (tima) channel registers (tach0h/l?ach3h/l) 254 channel status and control registers (tasc0?asc3) . . . . . . . . . . . 250 clock input pin (ptd3/taclk) . . . . . . . 245 counter modulo registers (tamodh:tamodl) . . . . . . . . 249 counter registers (tacnth/l) . . . 248 249 prescaler . . . . . . . . . . . . . . . . . . . . . . . 233 status and control register (tasc) . . . 246 timer interface module (timb) channel registers (tbch0h/l?bch3h/l) 278 channel status and control registers (tbsc0?bsc1) . . . . . . . . . . . 274 clock input pin (ptd3/tbclk) . . . . . . . 269 clock input pin (ptd4/tbclk) . . . . . . . 259 counter modulo registers (tbmodh/l) . . . 273 counter modulo registers (tbmodh:tb- modl) . . . . . . . . . . . . . . . . . . . 273 counter registers (tbcnth/l) . . . 272 273 counter registers (tbcnth:tbcntl) . 272 status and control register (tbsc) . . . . . . . 270 271 timer module characteristics . . . . . . . . . . . 388 tof bit (tim overflow flag bit) . . . . . 247 , 271 toie bit (tim overflow interrupt enable bit) . . 247 , 271 tovx bits (tim toggle on overflow bits) . 253 , f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 motorola index 415 277 trst bit (tim reset bit) . . . . . . .247 , 252 , 272 tstop bit (tim stop bit) . . . . . .247 , 252 , 271 txinv bit . . . . . . . . . . . . . . . . . . . . . . . . . .182 txinv bit (sci transmit inversion bit) 171 , 182 u user vectors addresses . . . . . . . . . . . . . . . . . . . . . . .32 v v bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 v dd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 v dda pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 vrs[7:4] ppg . . . . . . . . . . . . . . . . . . . . . . . . . . .110 v ss pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 w wait instruction 85 , 112 , 129 , 148 , 153 , 179 , 218 , 243 , 267 , 281 wait mode . . . . . . . . . . . . . . . . . . . .112 , 292 wait mode 129 , 148 , 153 , 179 , 218 , 243 , 267 , 281 wake bit (sci wake-up condition bit) . . . .183 web server . . . . . . . . . . . . . . . . . . . . . . . .418 web site . . . . . . . . . . . . . . . . . . . . . . . . . .418 x xld pbwc . . . . . . . . . . . . . . . . . . . . . . . . .108 z z bit ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC08AZ32 416 index motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 motorola literature updates 417 literature updates literature updates this document contains the latest data available at publication time. for updates, contact one of the centers listed below: literature distribution centers order literature by mail or phone. usa/europe motorola literature distribution p.o. box 5405 denver, colorado, 80217 phone 1-303-675-2140 us & canada only http://sps.motorola.com/mfax japan motorola japan ltd. tatsumi-spd-jldc toshikatsu otsuki 6f seibu-butsuryu center 3-14-2 tatsumi koto-ku tokyo 135, japan phone 03-3521-8315 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . literature updates MC68HC08AZ32 418 literature updates motorola hong kong motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong phone 852-26629298 customer focus center 1-800-521-6274 mfax to access this worldwide faxing service call or contact by electronic mail or the internet: rmfax0@email.sps.mot.com touch-tone 1-602-244-6609 http://sps.motorola.com/mfax motorola sps world marketing world wide web server use the internet to access motorola? world wide web server. use the following url: http://design-net.com microcontroller division?s web site directly access the microcontroller division? web site with the following url: http://design-net.com/csic/csic_home.html f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32 technical data customer response survey to make m68hc08 documentation as clear, complete, and easy to use as possible, we need your comments. please complete this form and return it by mail, or fax it to 512-891-3236. 1. how do you rate the quality of this document? 2. what is your intended use for this document? 3. does this document help you to perform your job? 4. are you able to easily find the information you need? 5. does each section of the document provide you with enough information? high low high low organization tables readability table of contents accuracy page size/binding figures overall impression comments: device selection for new application other please specify: system design training ye s n o comments: ye s n o comments: yes no yes no introduction spi module memory tima ram timb rom pit eeprom adc cpu keyboard interrupt module system integration module i/o ports clock generator module mscan08 controller mask options speci?ations break module appendix a monitor rom appendix b cop module appendix c lvi module glossary irq module index sci module 6. what would you like us to do to improve this document? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . first: cut along this line to remove motorola 6501 william cannon drive west mail stop oe17 austin, texas 78735-8598 attn: csic publications department second: fold back along this line please supply the following information (optional). name: ___________________________________________________ company name: ___________________________________________ title: ____________________________________________________ address: _________________________________________________ city: _____________________________state: _____zip:__________ phone number: ____________________________________________ microcontroller division f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC08AZ32/d motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. how to reach us: usa/europe: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 mfax: rmfax0@email.sps.mot.com C touchtone 1- 602-244-6609, http://sps.motorola.com/mfax us & canada only: http://sps.motorola.com/mfax home page: http://motorola.com/sps/ japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu, minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. 852-26668334 customer focus center: 1-800-521-6274 mfax is a trademark of motorola, inc. ? motorola, inc., 1999 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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